REVISION E 2/18/15
8761 DATA SHEET
13 LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TSSOP
T
ABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BCD
MINIMUM NOMINAL MAXIMUM
N
64
A
-- -- 1.60
A1
0.05 -- 0.15
A2
1.35 1.40 1.45
b
0.17 -- 0.27
c
0.09 -- 0.20
D
12.00 BASIC
D1
10.00 BASIC
D2
7.50 Ref.
E
12.00 BASIC
E1
10.00 BASIC
E2
7.50 Ref.
e
0.50 BASIC
L
0.45 -- 0.75
θ
0°
--
7°
ccc
-- -- 0.08
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
8761 DATA SHEET
14 REVISION E 2/18/15
TABLE 10. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature
8761CYLF ICS8761CYLF 64 Lead “Lead-Free” LQFP tray 0°C to 85°C
8761CYLFT ICS8761CYLF 64 Lead “Lead-Free” LQFP tape & reel 0°C to 85°C
NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
REVISION E 2/18/15
8761 DATA SHEET
15 LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
REVISION HISTORY SHEET
Rev Table Page Description of Change Date
A T1 2 Pin Description Table, revised Master Reset description. 8/15/02
A
T1
T4B, T4D
2
6, 8
Pin Description Table, pin 43 should be labeled at a PULLUP instead of a PULL-
DOWN.
LVCMOS DC Characteristics table -in the I
IH
and I
IL
rows, FBDIV_SEL0 was
deleted from the “pulldown” row and was added to the “pullup” row.
11/05/02
B
T3D
T5A, T5B
1
4
7, 9
Features section, changed max. output frequency from 200MHz to 183.3MHz,
and max. REF_CLK input frequency from 100MHz to 91.6MHz.
Control Function Table - revised Reference Frequency Range column and Fre-
quency columns to refl ect the output frequency change.
AC Characteristics tables - changed Output Frequency from 200MHz max. to
183.3MHz max.
11/06/02
B
T1
T5A, T5B
2
7, 9
10
11
Pin Description Table, revised crystal description.
AC Characteristics tables - changed Period Jitter measurement to
Period Jitter, RMS and added NOTE 8.
Added Crystal information.
Added Schematic Example in the Application Information Section.
1/20/03
B
T1
T4A, T4C
2
5, 7
10
10
Pin Description Table - revised MR description.
Power Supply Tables - changed V
DD
parameter to read “Core Supply Voltage”
from “Positive Supply Voltage”.
Deleted Crystal Input Interface section.
Updated Schematic Example diagram.
3/25/03
C
T3D
T4A
T5A & T5B
1
4
5
6 & 8
Updated Features to refl ect T5A, 3.3V AC Characteristics (see below).
Adjusted Ref. Frequency Range and Frequency columns.
Changed I
DD
max. from 150mA to 175mA, I
DDA
max. from 50mA to 55mA, and
I
DDO
max. from 330mA to 25mA.
Changed f
MAX
from 183.3MHz max. to 166.67MHz max.
Changed RMS tjit(per) from 20ps max. to 17ps max.
4/10/03
C
1
10
14
Features Section - added Lead-Free bullet.
Added Crystal Section.
Ordering Information Table - added Lead-Free/Annealed Part Number.
8/2/04
C 14 Ordering Information Table - added Lead-Free Part Number. 8/7/04
D
T2
T5
T10
3
6
9
10
11
14
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Crystal Characteristics Table - added Drive Level.
Power Supply Filtering Techniques - corrected last sentence in the paragraph to
read “”Figure 1 illustrates how a ferrite bead along...”” from
“”Figure 1 illustrates how a 10W resistor along...””.
Corrected Power Supply Filtering diagram.
Added Recommendations for Unused Input and Output Pins.
Corrected Schematic Example diagram.
Ordering Information Table - added Lead-Free note.
1/13/06
E
T10
14
16
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefi x from Part/Order Number column.
Added Contact Page.
7/26/10
E T10 14 Ordering Information - removed leaded devices PDN CQ-13-02 2/18/15

8761CYLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 17 LVCMOS OUT CLOCK GEN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet