MAX8633–MAX8636
Dual 300mA Pin-Programmable LDO
Linear Regulators
6 _______________________________________________________________________________________
Pin Description
PIN
MAX8633 MAX8634 MAX8635 MAX8636
NAME FUNCTION
1111IN
Regulator Input. Supply voltage from 2.7V to 5.5V.
Bypass IN with a ceramic capacitor of at least 2.2µF to
GND (see the Capacitor Selection and Regulator
Stability section).
2——2SHDN
Shutdown Input, Active Low. Drive SHDN logic low to
shut down both regulators. Connect SHDN to IN or drive
logic high for normal operation (see the Power-On
Sequence (MAX8633/Max8636 Only) section).
—2 2—SHDN1
LDO1 Shutdown Input, Active Low. Drive SHDN1 logic
low to shut down OUT1. Connect SHDN1 to IN or drive
logic high for normal operation.
—3 5—SHDN2
LDO2 Shutdown Input, Active Low. Drive SHDN2 logic
low to shut down OUT2. Connect SHDN2 to IN or drive
logic high for normal operation.
3—3 3P2
Programming Input 2. The state of P1 and P2 selects
one of nine output-voltage options (see Tables 1, 3).
4—4 4P1
Programming Input 1. The state of P1 and P2 selects
one of nine output-voltage options (see Tables 1, 3).
—4———P
Programming Input. The state of P selects one of three
output-voltage options for the MAX8634 (see Table 2).
5———RESET
Reset Output, Active Low, Open Drain. RESET goes high
impedance 120ms (min) after V
OUT2
rises above 87% of
the nominal output voltage. RESET is forced logic low
when V
OUT2
is below 82.5% of the nominal output
voltage. Connect RESET to OUT1, OUT2, or another
voltage of V
IN
or lower with a pullup resistor.
—5—5BP
Reference Noise Bypass. Bypass BP to GND with a
0.01µF ceramic capacitor to reduce output noise.
6 6 6 6 GND Ground
7 7 7 7 OUT2
Regulator 2 Output. Guaranteed 300mA output current
(see the Calculating Maximum Output Power section).
Bypass OUT2 with a ceramic capacitor of at least 2.2µF
to GND (see the Capacitor Selection and Regulator
Stability section).
8 8 8 8 OUT1
Regulator 1 Output. Guaranteed 300mA output current
(see the Calculating Maximum Output Power section).
Bypass OUT1 with a ceramic capacitor of at least 2.2µF
to GND (see the Capacitor Selection and Regulator
Stability section).
EP* EP* EP* EP* EP
Exposed Paddle. Solder the exposed paddle to a large
pad or circuit-board ground plane to increase thermal
dissipation.