also specify the clock mode. When software shutdown is
asserted, the ADC continues to operate in the last speci-
fied clock mode until the conversion is complete. Then the
ADC powers down into a low quiescent-current state. In
internal clock mode, the interface remains active and con-
version results can be clocked out after the MAX1245 has
entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit, and
powers up the MAX1245. Following the start bit, the data
input word or control byte also determines clock mode
and power-down states. For example, if the DIN word
contains PD1 = 1, the chip remains powered up. If PD0 =
PD1 = 0, a power-down resumes after one conversion.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike the software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. SHDN also controls the clock
frequency in internal clock mode. Letting SHDN be open
sets the internal clock frequency to 1.5MHz. When
returning to normal operation with SHDN open, there is a
t
RC
delay of approximately 2MΩ x C
L
, where C
L
is the
capacitive loading on the SHDN pin. Pulling SHDN high
sets the internal clock frequency to 225kHz. This feature
eases the settling-time requirement for the reference
voltage.
External Reference
An external reference is required for the MAX1245. The
reference voltage range is 1V to V
DD
.
At VREF, the input impedance is a minimum of 18kΩ for
DC currents. During a conversion, the reference must
be able to deliver up to 250µA DC load current and
have an output impedance of 10Ω or less. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the VREF pin with a 0.1µF capacitor.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes using a 2.048V reference.
The external reference must have a temperature coefficient
of 4ppm/°C or less to achieve accuracy to within 1LSB over
the commercial temperature range of 0°C to +70°C.
Figure 14 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 15 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = 500µV (2.048V /
4096) for unipolar operation and 1LSB = 500µV
[(2.048V / 2 - -2.048V / 2) / 4096] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 16 shows the recommended system ground
connections. A single-point analog ground (“star”
ground point) should be established at AGND, sepa-
rate from the logic ground. Connect all other analog
grounds and DGND to the star ground. No other digital
system ground should be connected to this ground.
The ground return to the power supply for the star
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
16 ______________________________________________________________________________________
vs. CONVERSION RATE
