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PCK2111BD,157

P1-P3P4-P6P7-P9
Philips Semiconductors Product data
PCK21111:10 LVDS clock distribution device
2002 Dec 16
4
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
SYMBOL
PARAMETER LIMITS UNIT
V
CC
Supply voltage -0.3 to 2.8 V
I
OSD
Driver short circuit current continuous
ESD Electrostatic discharge (Human Body Model 1.5 kΩ, 100 pF) >2 kV
T
j
Junction temperature 150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN MAX UNIT
V
CC
Supply voltage 2.375 2.625 V
V
IR
Receiver input voltage GND V
CC
T
amb
Operating ambient temperature range in free air -40 +85 °C
DC ELECTRICAL CHARACTERISTICS
T
amb
= -40 °C to +85 °C unless otherwise specified; V
CC
= 2.5 V ±5% (Notes 1, 2)
SYMBOL PARAMETER CONDITIONS MIN TYP
2
MAX UNIT
Driver
V
OD
Output differential voltage R
L
= 100 Ω 250 350 450 mV
∆V
OD
V
OD
magnitude change R
L
= 100 Ω — — 50 mV
V
OS
Offset voltage R
L
= 100 Ω 1.125 1.25 1.375 V
∆V
OS
V
OS
magnitude change R
L
= 100 Ω — — 50 mV
V
O
= 0 V — 15 40 mA
I
OSD
Output short circuit current
V
OD
= 0 V — 7 15 mA
Receiver
V
IDH
Input threshold HIGH — — 100 mV
V
IDL
Input threshold LOW -100 — — mV
V
IN
= 0 V — 50 100 µA
I
IN
Input current
V
IN
= V
CC
— 50 100 µA
Device
V
BB
Output reference voltage
V
CC
= 2.5 V;
I
OUT
≤ 100 µA
1.15 1.25 1.35 V
I
CCD
Power supply current
All drivers enabled and loaded;
input frequency = 800 MHz
— 190 230 mA
C
IN
Input capacitance V
IN
= 0 V to V
CC
— 5 — pF
C
OUT
Output capacitance — 5 — pF
V
IH
Logic input HIGH threshold V
CC
= 2.5 V 2 — — V
V
IL
Logic input LOW threshold V
CC
= 2.5 V — — 0.8 V
I
I
Logic input current
V
CC
= 2.5 V;
V
IN
= V
CC
or GND
— — ±10 µA
NOTES:
1. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
2. All typical values are given for V
CC
= +2.5 V and T
amb
= +25 °C, unless otherwise specified.
3. C
L
includes probe and fixture capacitance.
4. Generator waveforms for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50 Ω, 50% duty cycle.
5. The PCK2111 is a current mode device, and only functions to datasheet specifications when a resistive load is applied to the drives outputs.
Philips Semiconductors Product data
PCK21111:10 LVDS clock distribution device
2002 Dec 16
5
AC ELECTRICAL CHARACTERISTICS (LVDS)
T
amb
= -40 °C to +85 °C unless otherwise specified; V
CC
= 2.5 V ±5% (Note 1)
SYMBOL
PARAMETER CONDITIONS MIN TYP MAX UNIT
t
TLH
Transition time LOW to HIGH R
L
= 100 Ω; C
L
= 5 pF — 460 560 ps
t
THL
Transition time HIGH to LOW R
L
= 100 Ω; C
L
= 5 pF — 460 560 ps
t
PLH
t
PHL
Propagation delay to output — — 2 ns
f
MAX
Maximum input frequency 650 800 — MHz
Within-device skew — 35 — ps
t
skew
Part-to-part skew — 100 — ps
skew
Pulse skew — 50 — ps
t
JITTER
Cycle-to-cycle jitter — — 1 ps
NOTE:
1. Generator waveforms for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50 Ω, 50% duty cycle.
Philips Semiconductors Product data
PCK21111:10 LVDS clock distribution device
2002 Dec 16
6
CONTROL REGISTER SPECIFICATION
The PCK2111 is provided with an 11-bit shift register with a serial-in
and a Control Register. The purpose is to enable or power-off each
output clock channel and to select the clock input. The PCK2111
provides two working modes: Programmed mode, and Standard
mode.
Programmed Mode (EN = 1)
The shift register has a serial input to load the working configuration.
Once the configuration is loaded with 11 clock pulses, another clock
pulse loads the configuration into the Control Register. To restart the
configuration of the shift register, a reset of the state machine must
be done with a clock pulse on CK, and the EN set to LOW. The
Control Register can be configured only one time after each reset.
D0 is the first bit shifted in, D10 is the last bit shifted in. Bit D0
controls Q9, D9 controls Q0, and D10 controls CLKIN.
Standard Mode (EN = 0)
In Standard Mode, the PCK2111 is not programmable. All clock
buffer outputs are enabled. The LVDS clock input is selected from
Clock0 or Clock1 with the SI pin, as shown in the Truth Table.
Table 1. Truth Table of State Machine Inputs
EN SI CK OUTPUT
L L X All outputs enabled,
Clock0 selected,
Control Register disabled.
L H X All outputs enabled,
Clock1 selected,
Control Register disabled.
H L First stage stores “L”, other
stages store the data of
previous stage.
H H First stage stores “H”, other
stages store the data of
previous stage.
L X Reset of the state machine,
Shift register, and Control
Register.
Table 2. Configuration of the Control Register
Control Register bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Function Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CLK_SEL
Table 3. Truth Table of the Control Register
D10 Dn[0:9] Qn[0:9]
L H Clock0
H H Clock1
X L Qn output disabled
X = Don’t Care
AC ELECTRICAL CHARACTERISTICS (Control Register)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
f
MAX
Maximum frequency of shift register 50 — — MHz
t
s
Clock to SI setup time — — 4.0 ns
t
h
Clock to SI hold time — — 1.0 ns
t
rem
Enable to clock removal time — — 4.0 ns
t
w
Minimum clock pulse width 5 — — ns
P1-P3P4-P6P7-P9

PCK2111BD,157

Mfr. #:
Buy PCK2111BD,157
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 2:10 800MHZ 32LQFP
Lifecycle:
New from this manufacturer.
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