8305AGI www.idt.com REV. B SEPTEMBER 17, 2012
10
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 2
shows how a differential input can be wired to accept single ended
levels. The reference voltage V
1
= V
DD
/2 is generated by the bias resistors R1
and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias.
This bias circuit should be located as close to the input pin as possible. The ratio
of R1 and R2 might need to be adjusted to position the V
1
in the center of the
input voltage swing. For example, if the input clock swing is 2.5V and
V
DD
= 3.3V, R1 and R2 value should be adjusted to set V
1
at 1.25V. The values
below are for when both the single ended swing and V
DD
are at the same voltage.
This configuration requires that the sum of the output impedance of the driver
(Ro) and the series resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the input will attenuate the signal in half. This
can be done in one of two ways. First, R3 and R4 in parallel should equal the
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
transmission line impedance. For most 50
Ω
applications, R3 and R4 can be
100
Ω
. The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended signaling, the
noise rejection benefits of differential signaling are reduced. Even though the
differential input can handle full rail LVCMOS signaling, it is recommended that
the amplitude be reduced. The datasheet specifies a lower differential ampli-
tude, however this only applies to differential signals. For single-ended applica-
tions, the swing can be larger, however V
IL
cannot be less than -0.3V and V
IH
cannot be more than V
DD
+ 0.3V. Though some of the recommended compo-
nents might not be used, the pads should be placed in the layout. They can be
utilized for debugging purposes. The datasheet specifications are characterized
and guaranteed by using a differential signal.
RECOMMENDATION FOR UNUSED INPUT AND OUTPUT PINS
Inputs:
LVCMOS_CLK Input
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional protec-
tion, a 1kΩ resistor can be tied from the LVCMOS_CLK input
to ground.
CLK/nCLK Inputs
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; addi-
tional resistance is not required but can be added for addi-
tional protection. A 1kΩ resistor can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. There should
be no trace attached.
