®
AS7C4098A
2/21/06, v 1.2 Alliance Semiconductor P. 7 of 11
Write waveform 3
9
AC test conditions
Notes
1During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2 For test conditions, see AC Test Conditions, Figures A and B.
3t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
4 This parameter is guaranteed, but not tested.
5WE
is High for read cycle.
6CE
and OE are Low for read cycle.
7 Address valid prior to or coincident with CE
transition Low.
8 All read cycle timings are referenced from the last valid address to the first transitioning address.
9 All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C = 30 pF, except on High Z and Low Z parameters, where C = 5 pF.
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
WZ
t
AH
Data
OUT
Data undefined
High Z High Z
t
AS
t
AW
Data valid
t
WR
- Output load: see Figure B.
- Input pulse level: GND to V
CC
- 0.5V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
V
CC -
0.5V
2 ns
Figure A: Input pulse
255
Ω
C
10
480
Ω
D
OUT
GND
+5.0V
Figure B:5.0V Output load
168
Ω
D
OUT
+1.728V
Thevenin equivalent:
