ISL22512WFRU10Z-TK

10
FN6679.3
October 12, 2015
Shutdown Mode
The ISL22512 enters into Shutdown Mode if both PU and
PD
inputs are kept LOW for 2 seconds. In this mode, the
resistors array is totally disconnected from its RH pin and the
wiper is moved to position closest to RL pin, as shown in
Figure 13. Note, that PU
and PD inputs must be pulled LOW
within t
DB
time window of 15ms, see “Shutdown Mode
Timing” on page 6. Otherwise all command will be ignored till
both inputs will be released.
Holding either PU
, PD or ASE input LOW for more than
15ms will exit shutdown mode and return wiper to prior
shutdown position. If PU
or PD will be held LOW for more
than 250ms, the ISL22512 will start auto-increment or
auto-decrement of wiper position.
R
TOTAL
with V
CC
Removed
The end- to-end resistance of the array will fluctuate once
V
CC
is removed.
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RL
RW
RH
FIGURE 13. DCP CONNECTION IN SHUTDOWN MODE
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure
you have the latest Rev.
DATE REVISION CHANGE
10/12/15 FN6679.3 Updated the Ordering Information Table on page 2.
Added About Intersil section.
Updated the Package Outline Drawing M8.15 to the latest revision. Changes are as follows:
-Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern.
-Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-Changed Note 1 “1982” to “1994”
07/06/09 FN6679.2 Added reliability information on page 1 under Features and EEPROM Specifications in DC Electrical Spec
Table.
Changed Tja for 8 LD SOIC from “120” to “125”
Added Revision History
07/17/08 FN6679.1 1. Removed U option specs from table as there is no U option for this device.
2. Updated Pb-free note to new verbiage.
03/24/08 FN6679.0 Initial Release to web
ISL22512
11
FN6679.3
October 12, 2015
ISL22512
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
4
5
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6679.3
October 12, 2015
ISL22512
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
2
0.10 M C A B
0.05 M C
(ND-1) X e
C
0.05 C
A
0.10 C
A1
SEATING PLANE
e
INDEX AREA
PIN #1 ID
3
5
(DATUM A)
(DATUM B)
N-1
1
N
NX L
NX b
21
N
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
CC
5
C
L
TERMINAL TIP
(A1)
L
DETAIL “A” PIN 1 ID
L
0.05 MIN
0.10 MIN
0.10 C
2X
4xk
b
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.45 0.50 0.55 -
A1 - - 0.05 -
A3 0.127 REF -
b 0.15 0.20 0.25 5
D 2.05 2.10 2.15 -
E 1.55 1.60 1.65 -
e 0.50 BSC -
k0.20
---
L 0.35 0.40 0.45 -
N102
Nd 4 3
Ne 1 3
0-12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.00
0.80
1.75
0.25
0.50
0.275
2.50
LAND PATTERN
10

ISL22512WFRU10Z-TK

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs DCP 2 1 X 1 6
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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