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PT7C4511WE

P1-P3P4-P5
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PLL Clock Multiplier
2014-08-0004 PT0138-5 08/14/14
1
PT7C4511
Features
Zero ppm multiplication error
Input crystal frequency of 5 - 30 MHz
Input clock frequency of 1 - 50 MHz
Output clock frequencies up to 200 MHz
Peak to Peak Jitter less than 200ps over 200ns
interval (100~200MHz)
Low period jitter 50ps (100~200MHz)
9 selectable frequencies controlled by S0, S1 pins
Operating voltages of 3.0 to 5.5V
Tri-state output for board level testing
Lead free SOIC-8 package
Pin Configuration
1
2
3
X1/ICLK
GND
S1
4 5
6
7
8
Vcc
S0
CLK
OE
X2
SOIC-8 package
Description
The PT7C4511 is a high performance frequency
multiplier, which integrates Analog Phase Lock Loop
techniques.
The PT7C4511 is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most electronic
systems, clock multiplier and frequency translation.
Using Phase-Locked-Loop (PLL) techniques, the device
uses a standard fundamental mode, inexpensive crystal
to produce output clocks up to 200 MHz.
The complex Logic divider is the ability to generate nine
different popular multiplication factors, allowing one
chip to output many common frequencies.
The device also has an Output Enable pin that tri-states
the clock output when the OE pin is taken low. This
product is intended for clock generation and frequency
translation with low output jitter (variation in the output
period).
Pin Description
Name
Pin No.
Type
Description
X1/ICLK
1
X1
Crystal connection or clock input.
Vcc
2
P
Connect to +3.3V or +5V.
GND
3
P
Connect to ground.
S1
4
T1
Multiplier select pin, connect to
GND or Vcc or floating (no
connection).
CLK
5
O
Clock output per Table below.
S0
6
T1
Multiplier select pin 0, connect to
GND or Vcc or floating (no
connection).
OE
7
I
Output enable, tri-state CLK
output when low. Internal pull-up.
X2
8
XO
Crystal connection. Leave
unconnected for clock input.
Clock Output Table
S1
S0
0
0
0
M
0
1
M
0
M
M
M
1
1
0
1
M
1
1
1) Note: CLK output frequency=ICLK×4.
2) Note: M=Leave unconnected (self-biases to
Vcc/2).
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2014-08-0004 PT0138-5 08/14/14
2
PT7C4511
PLL Clock Multiplier
Block Diagram
PLL Clock Synthesis
and
Control Circuit
Crystal
Oscillator
S0
S1
X2
CLK
V
CC
GND
X1/ICLK
Output
Buffer
OE
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
PT7C4511 must be isolated from system power supply
noise to perform optimally. A decoupling capacitor of
0.01μF or 0.1uF must be connected between VCC and
the GND. It must be connected close to the PT7C4511
to minimize lead inductance. No external power supply
filtering is required for the PT7C4511.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the
CLK pin for trace lengths over one inch.
Crystal Load Capacitors
There is no on-chip capacitance build-in chip. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground. The value (in pF) of these crystal
caps should equal C
L
*2. In this equation, C
L
= crystal
load capacitance in pF. Example: For a crystal with a 15
pF load capacitance, each crystal capacitor would be
30pF.
Maximum Ratings
Storage Temperature ..................................................................................... - 65
o
C to +150
o
C
Ambient Operating Temperature ................................................................... -40
o
C to +85
o
C
Supply Voltage to Ground Potential (V
CC
) ................................................... - 0.3V to +7.0V
Inputs(Referenced to GND) ............................................. -0.5V to V
CC
+0.5V
Clock Output(Referenced to GND) ................................ -0.5V to V
CC
+0.5V
Recommended Operating Conditions
Sym
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
Supply voltage
-
3.0
-
5.5
V
T
A
Operating temperature
-
-40
-
+85
°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect reliability.
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2014-08-0004 PT0138-5 08/14/14
3
PT7C4511
PLL Clock Multiplier
DC Electrical Characteristics
(V
CC
= 3.3V±0.3V, T
A
= -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Test Condition
Pin
Min.
Typ.
Max.
Unit
Vcc
Supply Voltage
-
Vcc
3
3.3
3.6
V
Icc
Supply Current
no load, 20MHz
crystal,100MHz output
Vcc
-
12
20
mA
V
IH
Input Logic High
-
ICLK
(Vcc/2)+1
Vcc/2
-
V
OE
2
-
-
V
V
IL
Input Logic Low
-
ICLK
-
Vcc/2
(Vcc/2)-
1
V
OE
-
-
0.8
V
V
IH
Input Logic High
-
S0, S1
Vcc-0.5
-
-
V
V
IM
Input mid-level
-
S0, S1
-
Vcc/2
-
V
V
IL
Input Logic Low
-
S0, S1
-
-
0.5
V
V
OH
High-level output voltage
I
OH
= -12mA
CLK
2.4
-
-
V
V
OL
Low-level output voltage
I
OL
= 12mA
CLK
-
-
0.4
V
R
Internal pull up resistance
-
OE
-
270
-
k
I
S
Short Circuit Current
-
CLK
-
30
-
mA
(V
CC
= 5.0V±0.5V, T
A
= -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Test Condition
Pin
Min.
Typ.
Max.
Unit
Vcc
Supply Voltage
-
Vcc
4.5
5.0
5.5
V
Icc
Supply Current
no load, 20MHz
crystal,100MHz output
Vcc
-
20
30
mA
V
IH
Input Logic High
-
ICLK
(Vcc/2)+1
Vcc/2
-
V
OE
0.65*Vcc
-
-
V
V
IL
Input Logic Low
-
ICLK
-
Vcc/2
(Vcc/2)-
1
V
OE
-
-
0.8
V
V
IH
Input Logic High
-
S0, S1
Vcc-0.4
-
-
V
V
IM
Input mid-level
-
S0, S1
-
Vcc/2
-
V
V
IL
Input Logic Low
-
S0, S1
-
-
0.4
V
V
OH
High-level output voltage
I
OH
= -12mA
CLK
Vcc-0.5
-
-
V
V
OL
Low-level output voltage
I
OL
= 12mA
CLK
-
-
0.4
V
R
Internal pull up resistance
-
OE
-
270
-
k
I
S
Short Circuit Current
-
CLK
-
70
-
mA
P1-P3P4-P5

PT7C4511WE

Mfr. #:
Buy PT7C4511WE
Manufacturer:
Diodes Incorporated
Description:
Clock Generators & Support Products PLL Clock Multiplier
Lifecycle:
New from this manufacturer.
Delivery:
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