Table 14: DDR2 I
DD
Specifications and Conditions (Die Revision E) – 1GB (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol
-80E/
-800 -667 -53E -40E Units
Operating bank interleave read current: All device banks interleaving
reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK
=
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
I
DD7
3015 2520 2430 2340 mA
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM
I
DD
Specifications
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htf9c32_64_128x72ay – Rev. F 3/10 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 15: SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage V
DDSPD
1.7 3.6 V
Input high voltage: logic 1; All inputs V
IH
V
DDSPD
× 0.7 V
DDSPD
+ 0.5 V
Input low voltage: logic 0; All inputs V
IL
–0.6 V
DDSPD
× 0.3 V
Output low voltage: I
OUT
= 3mA V
OL
0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.1 3 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 3 µA
Standby current I
SB
1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz I
CCR
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz I
CCW
2 3 mA
Table 16: SPD EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time bus must be free before a new transition can start
t
BUF 1.3
µs
Data-out hold time
t
DH 200
ns
SDA and SCL fall time
t
F
300 ns 2
SDA and SCL rise time
t
R
300 ns 2
Data-in hold time
t
HD:DAT 0
µs
Start condition hold time
t
HD:STA 0.6
µs
Clock HIGH period
t
HIGH 0.6
µs
Noise suppression time constant at SCL, SDA inputs
t
I
50 µs
Clock LOW period
t
LOW 1.3
µs
SCL clock frequency
t
SCL
400 kHz
Data-in setup time
t
SU:DAT 100
ns
Start condition setup time
t
SU:STA 0.6
µs 3
Stop condition setup time
t
SU:STO 0.6
µs
WRITE cycle time
t
WRC
10 ms 4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM
Serial Presence-Detect
PDF: 09005aef80e8ad4d
htf9c32_64_128x72ay – Rev. F 3/10 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 3: 240-Pin DDR2 UDIMM
30.50 (1.20)
29.85 (1.175)
Pin 1
17.78 (0.70)
TYP
2.50 (0.098) D
(2X)
2.30 (0.091) TYP
5.0 (0.197) TYP
123.0 (4.840)
TYP
1.0 (0.039)
TYP
0.80 (0.031)
TYP
2.00 (0.079) R
(4X)
0.76 (0.030) R
Pin 120
Front view
133.50 (5.256)
133.20 (5.244)
55.0 (2.165)
TYP
63.0 (2.48)
TYP
10.00 (0.394)
TYP
Back view
Pin 240
Pin 121
1.37 (0.054)
1.17 (0.046)
2.70 (0.106)
MAX
U1
U2 U3 U4
U10
U6 U7 U8 U9
No components this side of module
2.21 (0.087) TYP
1.0 (0.039) TYP
3.04 (0.1197) TYP
70.66 (2.782)
TYP
U5
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for
additional design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM
Module Dimensions
PDF: 09005aef80e8ad4d
htf9c32_64_128x72ay – Rev. F 3/10 EN
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.

MT9HTF12872AY-40EA1

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 1GB 240UDIMM
Lifecycle:
New from this manufacturer.
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