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CAT1025YI-25-GT3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
CAT1024, CAT1025
Doc. No. MD-3008 Rev. R 10 © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
ACKNOWLEDGE
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
The CAT1024/25 responds with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with
a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT1024/25 begins a READ mode it
transmits 8 bits of data, releases the SDA line and
monitors the line for an acknowledge. Once it
receives this acknowledge, the CAT1024/25 will
continue to transmit data. If no acknowledge is sent
by the Master, the device terminates data transmis–
sion and waits for a STOP condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W
¯¯
bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknow-
ledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The CAT1024/25 acknowledges once more and the
Master generates the STOP condition. At this time, the
device begins an internal programming cycle to non-
volatile memory. While the cycle is in progress,
the device will not respond to any request from the
Master device.
Figure 5. Start/Stop Timing
Figure 6. Acknowledge Timing
Figure 7: Slave Address Bits
START BIT
SD
A
STOP BIT
SCL
ACKNOWLEDGE
1
STA
R
T
SCL FROM
MASTER
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
1 0100 00R/W
Default Configuration
CAT1024, CAT1025
© 2009 SCILLC. All rights reserved. 11 Doc. No. MD-3008 Rev. R
Characteristics subject to change without notice
Page Write
The CAT1024/25 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of
terminating after the initial byte is transmitted, the
Master is allowed to send up to 15 additional bytes.
After each byte has been transmitted, the CAT1024/25
will respond with an acknowledge and internally
increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1024/25 in a single write cycle.
Figure 8. Byte Write Timing
Figure 9: Page Write Timing
BYTE
ADDRESS
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+15
BYTE
ADDRESS (n)
A
C
K
A
C
K
DATA n
A
C
K
S
T
O
P
S
A
C
K
DATA n+1
A
C
K
S
T
A
R
T
P
SLAVE
ADDRESS
CAT1024, CAT1025
Doc. No. MD-3008 Rev. R 12 © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1024/25 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the device is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1025 only) allows
the user to protect against inadvertent memory array
programming. If the WP pin is tied to V
CC
, the entire
memory array is protected and becomes read only.
The CAT1025 will accept both slave and byte addre-
sses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT1024/25 is initiated in the
same manner as the write operation with one exception,
the R/W
¯¯
bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Figure 10. Immediate Address Read Timing
SCL
SDA 8TH BI T
STOPNO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
BUS ACTIVIT Y:
MASTER
SDA LINE
S
T
A
R
T
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

CAT1025YI-25-GT3

Mfr. #:
Buy CAT1025YI-25-GT3
Manufacturer:
ON Semiconductor
Description:
Supervisory Circuits CPU SUP W/2K EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
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