Si5351A/B/C
30 Preliminary Rev. 0.95
Reset value = 0000 0000
Register 16. CLK0 Control
BitD7D6D5D4D3D2D1D0
Name
CLK0_PDN MS0_INT MS0_SRC CLK0_INV CLK0_SRC[1:0] CLK0_IDRV[1:0]
Type
R/W R/W R/W R/W R/W R/W
Bit Name Function
7 CLK0_PDN Clock 0 Power Down.
This bit allows powering down the CLK0 output driver to conserve power when the out-
put is unused.
0: CLK0 is powered up.
1: CLK0 is powered down.
6MS0_INTMultiSynth 0 Integer Mode.
This bit can be used to force MS0 into Integer mode to improve jitter performance. Note
that the fractional mode is necessary when a delay offset is specified for CLK0.
0: MS0 operates in fractional division mode.
1: MS0 operates in integer mode.
5MS0_SRCMultiSynth Source Select for CLK0.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
4 CLK0_INV Output Clock 0 Invert.
0: Output Clock 0 is not inverted.
1: Output Clock 0 is inverted.
3:2 CLK0_SRC[1:0] Output Clock 0 Input Source.
These bits determine the input source for CLK0.
00: Select the XTAL as the clock source for CLK0. This option by-passes both synthesis
stages (PLL/VCXO & MultiSynth) and connects CLK0 directly to the oscillator which
generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK0. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK0 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK0. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK0_IDRV[1:0] CLK0 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
