IDT 89HPES32NT8BG2 Datasheet
12 of 35 December 17, 2013
Reference Clocks GCLKN[1:0] I HCSL Diff. Clock
Input
Refer to Table 11
Note: Unused port
clock pins should be
connected to Vss on
the board.
GCLKP[1:0] I
P00CLKN I
P00CLKP I
P02CLKN I
P02CLKP I
P04CLKN I
P04CLKP I
SMBus MSMBCLK I/O LVTTL STI
3
Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specifica-
tion.
MSMBDAT I/O STI
SSMBADDR[2] I pull-up
SSMBCLK I/O STI Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specifica-
tion.
SSMBDAT I/O STI
General Purpose I/O GPIO[8:0] I/O LVTTL STI, High
Drive
pull-up Unused pins can be left
floating.
Stack Configuration STK0CFG0 I LVTTL Input pull-down Unused pins can be left
floating.
STK1CFG0 I
STK2CFG0 I
STK3CFG0 I
System Pins CLKMODE[1:0] I LVTTL Input pull-up Unused pins can be left
floating.
GCLKFSEL I pull-down
PERSTN I Schmitt trigger
RSTHALT I pull-down Unused pins can be left
floating.
SWMODE[3:0] I pull-down
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up Unused pins can be left
floating.
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up
SerDes Reference Resis-
tors
REFRES[7:0] — Analog Unused pins should be
connected to Vss on
the board.
REFRESPLL —
1.
Internal resistor values under typical operating conditions are 92K for pull-up and 91K for pull-down.
2.
All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3.
Schmitt Trigger Input (STI).
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 10 Pin Characteristics (Part 2 of 2)