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AT17F32A-30BJU

P1-P3P4-P6P7-P9P10-P12P13-P14
Features
• Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability
• 5V Tolerant I/O Pins
• Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
• In-System Programmable (ISP) via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Altera
®
FLEX
®
, Excalibur
™
, Stratix
™
, Cyclone
™
and APEX
™
Devices
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Low-power CMOS FLASH Process
• Available in 44 PLCC Packages
• Emulation of Atmel’s AT24Cxxx Serial EEPROMs
• Low-power Standby Mode
• Single Device Capable of Holding 4 Individual Bit Stream Files Allowing Simple System
Reconfiguration
• Endurance: 10,000 Write Cycles Typical
• Green (Lead and Halide-Free/ROHS Compliant) Package Options Available
1. Description
The AT17FxxA Series of In-System Programmable Configuration PROMs (Configura-
tors) provide an easy-to-use, cost-effective configuration memory for Field
Programmable Gate Arrays. The AT17FxxA Series device is packaged in the 44-lead
PLCC see Table 1-1. The AT17FxxA Series Configurator uses a simple serial-access
procedure to configure one or more FPGA devices.
The AT17FxxA Series Configurators can be programmed with industry-standard pro-
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1. AT17FxxA Series Packages
Package AT17F32A
44-lead PLCC Yes
FPGA
Configuration
Flash Memory
AT17F32A
3489C–CNFG–08/07
2
3489C–CNFG–08/07
AT17F32A
2. Pin Configuration
44-lead PLCC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
NC
GND
PAGESEL0
NC
NC
NC
NC
NC
NC
NC
nCASC/A2
NC
NC
NC
NC
DATA
PAGE_EN
NC
NC
NC
VCC
NC
NC
DCLK
NC
NC
NC
NC
NC
NC
NC
RESET/OE
nCS
NC
SER_EN
NC
NC
READY
NC
PAGESEL1
NC
NC
NC
NC
3
3489C–CNFG–08/07
AT17F32A
3. Block Diagram
4. Device Description
The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET
/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET
/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17FxxA
Series Configurator. If nCS is held High after the RESET
/OE reset pulse, the counter is disabled
and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the
DATA output pin are enabled. When RESET
/OE is driven Low again, the address counter is
reset and the DATA output pin is tri-stated, regardless of the state of nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other configurators. Upon power-up, the address
counter is automatically reset.
Config. Page
Select
Power-on
Reset
Flash
Memory
Clock/Oscillator
Logic
2-wire Serial Programming
Serial Download Logic
Control Logic
DCLK
nCASC(A2)
DATA
nCS
RESET/OE
SER_EN
CE/WE/OE
Data
Address
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset
P1-P3P4-P6P7-P9P10-P12P13-P14

AT17F32A-30BJU

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Description:
IC EEPROM FLASH 32MBIT 44-PLCC
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