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ICL7116CJL

P1-P3P4-P6P7-P8
Specifications below satisfy or exceed all ‘tested’ parameters on adjacent page V
+
= 9V, T
A
= +25ºC, f
CLOCK
= 48kHz; test circuit =
Figure 1 (ICL7116), Figure 2 (ICL7117), unless otherwise noted.)
Note 7: Test condition is V
IN
applied between pins IN HI and IN LO i.e., 1MΩ resistor in Figure 1 and Figure 2.
Note 8: All pins are designed to withstand electrostatic discharge (ESD) levels in excess of 2000V (Test circuit per MIL. Std. 883C.
Method 3015 2).
Note 9: Input voltages may exceed the supply voltage provided the input current is limited to ±1mA (This revises Note 1 on the
adjacent page).
Note 10: Number of measurement cycles for display to give accurate reading.
Note 11: 1MΩ resistor is removed in Figure 1 and Figure 2.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Common-Mode Rejection Ratio (Note 4)
V
CM
= ±1V, V
IN
= 0V
Full Scale = 200.00mV
50 µV/V
Noise (Pk-Pk Value Not Exceeded 95%
of the Time)
V
IN
= 0V
Full Scale = 200.00mV
15 µV
Input Leakage Current
V
IN
= 0V, T
A
= +25°C (Note 7) 1 10
pA
0°C ≤ T
A
≤ +70°C 20 200
Zero Reading Drift V
IN
= 0V, 0°C ≤ T
A
≤ +70°C 0.2 1 µV/°C
Scale Factor Temperature Coefcient
V
IN
= 199.0mV
0°C ≤ T
A
≤ +70°C
(Ext. Ref. 0ppm/°C)
1 5 ppm/°C
V+ Supply Current (Does Not Include LED
Current for ICL7117)
V
IN
= 0V, T
A
= +25°C 0.8 1.8
mA
0°C ≤ T
A
≤ +70°C 2
V- Supply Current for ICL7117 Only 0.6 1.8 mA
Analog Common Voltage (With Respect to
Positive Supply)
25Ω Between Common and Positive Supply 2.4 2.8 3.2 V
Temperature Coefcient of Analog Common
(With Respect to Pos. Supply)
25Ω Between Common and Positive Supply 80 ppm/°C
Input Resistance, Pin 1 (Note 6) 30 70 kΩ
V
IL
, Pin 1 (ICL7116 Only) TEST + 1.5 V
V
IL
, Pin 1 (ICL7117 Only) GND + 1.5 V
V
IH
, Pin 1 (Both) V+ - 1.5 V
ICL7116 Only (Note 5)
Pk-Pk Segment Drive Voltage,
Pk-Pk Backplane Drive Voltage
V+ to V- = 9V 4 5 6 V
ICL7117 Only (Except Pin 19) Segment
Sinking Current
V+ = 5.0V
Segment Voltage = 3V
5 8.0
mA
(Pin 19 Only) 10 16
ICL7116 Only – Test Pin Voltage With respect to V+ 4 5 6 V
Overload Recovery Time
(Note 10)
V
IN
changing from ±10V to 0V 0 1
Measur-
ement
Cycles
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
www.maximintegrated.com
Maxim Integrated
│
4
Electrical Characteristics (continued)
Detailed Description
The Maxim ICL7116 and ICL7117 3½ digit ADCs are
similar to the Maxim ICL7106 and ICL7107, except for the
addition of a Hold pin. For a detailed product description,
package dimensions, and applications information (other
than the operation of the Hold pin described below) refer
to Maxim’s ICL7106 and ICL7107 data sheet
Hold Input
The Hold input is a digital input with a logic threshold
approximately midway between V+ and Test (ICL7116)
or V+ and Ground (ICL7117). The ICL7116/ICL7117 con-
tinuously performs conversions, independent of the Hold
input. When the Hold input is connected to V+, however,
the display latch pulse is inhibited, and the the display
latches are not updated. The Hold input has a 70kΩ pull-
down resistor to Test (ICL7116) or Ground (ICL7117) and
the Hold input will be pulled low if it is left open. When
Hold is low the ICL7116/ICL7117 updates the display
at the end of each conversion. The Hold input is CMOS
compatible and can also be driven by a switch connected
to V
+
(Figure 1 and Figure 2) or by a PNP transistor.
Unlike the ICL7106 and the ICL7107, the ICL7116 and
ICL7117 do not have a Reference Low input. Apply the
reference voltage between Reference High (REF HI) and
Common.
Figure 1. Maxim ICL7116 Typical Operating Circuit, 200mV Reference
ANALOG
INPUT
ICL7116
+
-
LCD DISPLAY
V
REF
CLOSED = HOLD
OPEN = RUN
9V
TO ANALOG
COMMON PIN
[PIN 32]
IN HI
31
IN LO
30
32
1MΩ
0.01µF
COMMON
BUFF
28
A-Z
29
INT
29
0.47µF
0.22µF
47kΩ
39
34 33
0.1µF
C+REF C-REF
OSC
2
OSC
3
OSC
1
38
C
OSC
100pF
100kΩ
40
R
OSC
SEGMENT
DRIVE
2–19
22–25
POL
BP
20
21 MINUS SIGN
BACKPLANE
DRIVE
HOLD
1
V
+
V
-
REF HI
35
36
26
24kΩ
10kΩ
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
www.maximintegrated.com
Maxim Integrated
│
5
Figure 2. Maxim ICL7117 Typical Operating Circuit, 200mV Reference
D
3
E
2
F
2
A
2
B
2
C
2
D
2
E
1
G
1
F
1
B
3
F
3
E
3
AB
4
POL
4
BP/GND [7116/7117]
G
3
A
3
C
3
G
2
V
-
INT
BUFF
A/Z
IN LO
IN H1
COMMON
C
-
REF
C
+
REF
A
1
B
1
C
1
D
1
HLDR
OSC
1
OSC
2
OSC
3
TEST
REF HI
V
+
0.168"
(4.27mm)
0.130"
(3.30mm)
Chip Topography
ANALOG
INPUT
ICL7117
+
-
LCD DISPLAY
V
REF
CLOSED = HOLD
OPEN = RUN
TO ANALOG
COMMON PIN
[PIN 32]
IN HI
31
IN LO
30
32
1MΩ
0.01µF
COMMON
BUFF
28
A-Z
29
INT
29
0.47µF
0.22µF
47kΩ
39
34 33
0.1µF
C+REF C-REF
OSC
2
OSC
3
OSC
1
38
C
OSC
100pF
100kΩ
40
R
OSC
SEGMENT
DRIVE
2–19
22–25
POL
BP
20
21
BACKPLANE
DRIVE
1
V
+
V
-
REF HI
35
36
26
24kΩ
10kΩ
+5V
+5V
HOLD
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
www.maximintegrated.com
Maxim Integrated
│
6
P1-P3P4-P6P7-P8

ICL7116CJL

Mfr. #:
Buy ICL7116CJL
Manufacturer:
Maxim Integrated
Description:
IC DISPLAY DRVR 3.5DIG 40CERDIP
Lifecycle:
New from this manufacturer.
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