NCP6334B, NCP6334C
http://onsemi.com
13
LAYOUT CONSIDERATIONS
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and highfrequency loop area. It is also
good for efficiency improvement.
The device should be well decoupled by input capacitor
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
SW node should be a large copper pour, but compact
because it is also a noise source.
It would be good to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Directly connect AGND pin to the exposed pad
and then connect to AGND ground plane through vias.
Try best to avoid overlap of input ground loop and
output ground loop to prevent noise impact on output
regulation.
Arrange a “quiet” path for output voltage sense and
feedback network, and make it surrounded by a ground
plane.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
The exposed pad must be well soldered on the board.
A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
More free vias are welcome to be around IC and/or
underneath the exposed pad to connect the inner ground
layers to reduce thermal impedance.
Use large area copper especially in top layer to help
thermal conduction and radiation.
Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
A
VINGND
VOUT GND
Cin
Cin
L
Cout
Cout
O
2
4
FB
SW
3
AGND
7
5
EN
AVIN
6
MODE/PG
1
PGND
8
PVIN
F
O
A
Cfb
R1
R2
P P P
P
P
P
A
A
F
PPP
PPP
P
P
P
Figure 20. Recommended PCB Layout for Application Boards
NCP6334B, NCP6334C
http://onsemi.com
14
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511BE
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.10
C0.08
A1
SEATING
PLANE
8X
NOTE 3
b
8X
0.10 C
0.05 C
A
BB
DIM MIN MAX
MILLIMETERS
A 0.70 0.80
A1 0.00 0.05
b 0.20 0.30
D 2.00 BSC
D2 1.50 1.70
E 2.00 BSC
E2 0.80 1.00
e 0.50 BSC
L 0.20 0.40
1
4
8
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.00
2.30
1
DIMENSIONS: MILLIMETERS
0.50
8X
NOTE 4
0.30
8X
DETAIL A
A3 0.20 REF
A3
A
DETAIL B
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
A1
A3
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
L1 −−− 0.15
OUTLINE
PACKAGE
e
RECOMMENDED
K 0.25 REF
5
1.70
K
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Phone: 81358171050
NCP6334B/D
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NCP6334BMT26TBG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators USR BUCK CONVERTER
Lifecycle:
New from this manufacturer.
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