© Semiconductor Components Industries, LLC, 2007
March, 2007 Rev. 1
1 Publication Order Number:
74HC595/D
74HC595
8−Bit Serial−Input/Serial or
Parallel−Output Shift
Register with Latched
3−State Outputs
HighPerformance SiliconGate CMOS
The 74HC595 consists of an 8bit shift register and an 8bit Dtype
latch with threestate parallel outputs. The shift register accepts serial
data and provides a serial output. The shift register also provides
parallel data to the 8bit latch. The shift register and latch have
independent clock inputs. This device also has an asynchronous reset
for the shift register.
The HC595 directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
Improved Propagation Delays
50% Lower Quiescent Power
Improved Input Noise and Latchup Immunity
These are PbFree Devices
http://onsemi.com
MARKING
DIAGRAMS
HC595 = Device Code
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or = PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
1
16
1
16
HC
595
ALYW
1
16
1
16
HC595G
AWLYWW
(Note: Microdot may be in either location)
74HC595
http://onsemi.com
2
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
V
CC
= PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
ORDERING INFORMATION
Device Package Shipping
74HC595DR2G SOIC16
(PbFree)
2500 Tape & Reel
74HC595DTR2G TSSOP16* 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
74HC595
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package) 260
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating SOIC Package: – 7 mW/C from 65 to 125C
TSSOP Package: 6.1 mW/C from 65 to 125C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage
(Referenced to GND)
0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

74HC595DG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers SHIFT REGSTR 3-STATE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet