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NCP1601BDR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NCP1601A, NCP1601B
http://onsemi.com
10
FUNCTIONAL DESCRIPTION
Introduction
The NCP1601 is a Power Factor Correction (PFC) boost
controller designed to operate in Discontinuous
Conduction Mode (DCM) and Critical Conduction Mode
(CRM). The fixed--frequency nature of DCM limits the
maximum switching frequency. It limits the possible
conduct ed and radiated EMI noise that may pol lute
surrounding systems. NCP1601 offers the simplest solution
to PFC including fewer external circuit components and
simple voltage--mode feedba ck. The diode turn--off
switching loss is negligible and hence there is no need to
use a low reverse--recovery time t
rr
diode. On the other
hand, the CRM feature is added to limit the maximum
current stress to twice of the average current. The NCP1601
incorporates high safety protection features and combines
the a dvantage s of DCM and CRM so that the NCP1601 is
suitable for robust and compact PFC stages.
The NCP1601 provides the following protection features:
1. Overvoltage Protection (OVP) is activated and
the output drive goes low when the output voltage
exceeds 107% of the nominal regulation level
which is a user--defined value. The circuit
automatically resumes operation when the output
voltage becomes lower than 107%.
2. Undervoltage Protection (UVP) is activated and
the de vice is shut down when the output voltage
goes below 8% of the nominal regulation level.
The c ircuit automatically resumes operation when
the output voltage goes above 8% of the nominal
regulation level. This feature also provides output
open--l oop protection and external shutdown
feature.
3. Overcurrent Protection (OCP) is activated and
the output device goes low when the inductor
current exceeds a user--defined value. The
operation automatically resumes when the
inductor current becomes lower than this
user--defined value at the next clock cycle.
4. Thermal Shutdown (TSD) is activated and the
output drive is disabled when the junction
temperature exceeds 140C. The operation
resumes when the junction temperature falls
down by typical 45C.
The NCP1601 is available in two versions. The
NCP1601A has a typical 4.75 V undervoltage lockout
(UVLO) hysteresis, while NCP1601B has a typical 1.5 V
UVLO hysteresis. It allows the use of different V
CC
biasing
schemes.
Operating Modes of NCP1601
The NCP1601 is a PFC driver primarily designed to
operate in fixed--frequency DCM. In the most stressful
conditions, CRM can be an alternative option which is
without power factor degradation. On the other hand, the
NCP1601 ca n be viewed as a CRM controlle r with a
frequency clamp (maximum switching frequency limit)
alternative option which is also without power factor
degrada tion. In summary, the NCP1601 can cover both
CRM and DCM without power factor degradation. Based
on the selections of the boost inductor a nd the oscillator
frequency, the circuit is capable of the following three
applications.
1. “Mostly in CRM” with a frequency c lamp set by
the oscillator or synchronization frequency.
2. “Mostly in fixed--frequency mode DCM” and
only run in CRM at high load and low line.
3. “Fixed--frequency DCM” only.
Figure 25. Operating Modes
Inductor current, I
L
Input current, I
in
time
Current
DCMDCM Critical Mode
DCM needs higher peak inductor current comparing to
CRM in the same averaged input current. Hence, CRM is
genera lly preferred at around the sinusoidal peak for lower
the maximum current stress but DCM is also preferred at
the non--peak region to avoid excessive switching
frequencies. Because of the variable --frequency feature of
the CRM and constant--frequency feature of DCM,
switching frequency is the maximum in the DCM region
and hence the minimum switching frequency will be found
at the moment of the sinusoidal peak.
DCM PFC Circuit
A DCM/CRM PFC boost converter is shown in Figure 26.
Input voltage is a rectified 50 or 60 Hz sinusoidal signal. The
MOSF ET is switching at a high frequency (typically around
100 kHz) so that the inductor current I
L
basically consis ts of
high--frequency and low--frequency components.
Filter capacitor C
filter
is an essential and very small value
capacitor in order to eliminate the high--frequency content
of the DCM inductor current I
L
. This filter capacitor cannot
NCP1601A, NCP1601B
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11
be too bulky because it can pollute the power factor by
distorting the rectified sinusoidal input voltage.
Figure 26. DCM/CRM PFC Boost Converter
V
in
I
in
I
L
L
V
out
C
bulk
C
filter
PFC Methodology
NCP1601 uses a proprietary PFC methodology
particularly designed for both DCM and CRM operation.
The PFC methodology is described in this section.
Figure 27. Inductor Current in DCM
t
1
t
2
t
3
I
pk
T
time
Inductor Current
As shown in Figure 27, the inductor current I
L
of each
switching cycle starts from zero in DCM. CRM is a special
case of DCM when t
3
= 0. When the PFC boost converter
MOSFET is on, the inductor current I
L
increases from zero
to I
pk
for a time duration t
1
with inductance L and input
voltage V
in
. (eq.1) is formulated.
V
in
= L
I
pk
t
1
(eq.1)
The input filter capacitor C
filter
and the front--ended EMI
filter absorb the high--freque ncy component of inductor
current. It makes the input current I
in
a low--frequency
signal.
I
in
=
I
pk
(
t
1
+ t
2
)
2T
(eq.2a)for DCM
I
in
=
I
pk
2
(eq.2b)for CRM
From (eq.1) and (eq.2), the input impedance Z
in
is
formulated.
Z
in
=
V
in
I
in
=
2TL
t
1
(
t
1
+ t
2
)
(eq.3a)for DCM
Z
in
=
V
in
I
in
=
2L
t
1
(eq.3b)for CRM
Power fact or is corre cted when the input impedance Z
in
in (eq.3) are constant or slowly varying.
The MOSFET on time t
1
or PFC m odulat ion duty is
genera ted by a feedback signal V
ton
an d a ra m p . The PFC
modulation circuit and timing diagram are shown in
Figure 28. A rel ati onship in (eq.4) is obtai ned.
t
1
=
C
ramp
V
ton
I
ch
(eq.4)
Figure 28. PFC Modulation Circuit and Timing
Diagram
--
+
closed when
output low
PFC
Modulation
Turns off
MOSFET
Ramp
3
C
ramp
I
ch
V
ton
V
ton
ramp
output
The charging current I
ch
is consta nt 100 mA current and
the ramp capacitor C
ramp
is constant for a particular design.
Hence, according to (eq.4) the MOSFET on time t
1
is
proportional to V
ton
.
In order to protect the PFC m odulation comparator, the
maximum voltage of V
ton
is limited to internal clamp
V
ton(max)
(3.9 V typical) and the ramp pin (Pin 3) is with a
9 V ESD Zener diode. The 3.9 V maximum limit of this
V
ton
indirectly limits the maximum on time.
Figure 29. V
control
Processing Circuit
+
--
closed when zero current
2
C
control
V
control
R
1
R
2
R
3
C
1
C
3
V
ton
The V
control
processing circuit generates V
ton
from
control voltage V
control
and time information of zero
inductor current. The circuit in Figure 29 makes (eq.5)
where the value of resistor R
1
is much higher than the value
of resistor R
2
(R
1
>> R
2
).
V
ton
=
TV
control
t
1
+ t
2
(eq.5a)for DCM
NCP1601A, NCP1601B
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12
V
ton
= V
control
(eq.5b)for CRM
It is noted that V
ton
is always greater than or equal to
V
control
(i.e., V
ton
V
control
).
In summary, t he input impedance Z
in
in (eq.6) is obtained
from (eq.1) --(eq.5)
Z
in
=
V
in
I
in
=
2LI
ch
C
ramp
V
control
(eq.6)
Control voltage V
control
comes from the PFC output
voltage V
out
which is a slowly varying signal. The
bandwidth of V
control
can be additionally limited by
inserting an external capacitor C
control
to the V
control
pin
(Pin 2) in Figure 28. The internal 300 kΩ resistor and the
capacitor C
control
create a low--pass filter which has a
bandwidth f
control
in (eq.7). It is generally recommended to
limit the bandwidth below 20 Hz to achieve power factor
correc tion. Typical value of C
control
is 0.1 mF.
C
control
>
1
2π300kΩ f
control
(eq.7)
If the bandwidth of V
control
is much less than the 50 or
60 Hz line frequency, the input impedance Z
in
is slowly
varying or roughly constant. Then, t he power fac tor
correction is achieved in DCM and CRM.
Figure 30. V
control
Low--Pass Filtering
300k
Regulation Block
2
C
control
V
control
V
reg
I
ref
I
ref
96% I
FB
V
control
Processing
Circuit
Maximum Power
Input and output power (P
in
and P
out
) are derived in
(eq.8) when the circuit efficiency η is obtained or assumed.
ThevariableV
ac
stands for the RMS input voltage.
(eq.8a)
P
in
=
V
ac
2
Z
in
=
V
ac
2
C
ramp
V
control
2LI
ch
(eq.8b)
P
out
= η P
in
=
ηV
ac
2
C
ramp
V
control
2LI
ch
From (eq.8), control voltage V
control
controls the amount
of output power, input power, or input impedance. The
maximum value of the control voltage V
control
is 1.05 V
(i.e., V
control(max)
= 1.05 V). A parameter called maximum
power resistor R
power
(10.5 kΩ typical) is defined in (eq.9)
and restricted to have a maximum 10% variation
(i.e., 9.5 kΩ R
power
11.5 kΩ) for defining the maximum
power in an application.
R
power
=
V
control(max)
I
ch
=
1.05 V
100 mA
= 10.5 kΩ
(eq.9)
It means that the ma ximum input and output power
(P
in(max)
and P
out(max)
) a re limited to 10% variation.
(eq.10a)
P
in(max)
=
V
ac
2
C
ramp
R
power
2L
(eq.10b)
P
out(max)
=
ηV
ac
2
C
ramp
R
power
2L
The maximum input current I
ac(max)
to deliver the
maximum input power P
in(max)
is also derived in (eq.11).
The suffix ac stands for RMS value.
(eq.11)
I
ac(max)
=
P
in(max)
V
ac
=
V
acC
ramp
R
power
2L
Output Feedback
The output vol tage V
out
of the PFC circuit is sensed as a
feedback current I
FB
flowing into the FB pin (Pin 1) of the
devic e. The FB pin voltage V
FB1
is typically less than 5 V
referring to Figure 11. It is much lower than V
out
which is
typically 400 V. Therefore, V
FB1
is generally neglected.
(eq.12)
I
FB
=
V
out
− V
FB1
R
FB
≈
V
out
R
FB
where R
FB
is the feedback resistor connected between the
FB pin (Pin 1) and the output voltage referring to Figure 2.
Then, the feedback current I
FB
represents t he output
voltage V
out
and will be used in the output voltage
regulation, Undervoltage Protection (UVP), and
Overvoltage Protection (OVP).
Output Voltage Regulation
Feedback current I
FB
, which presents output voltage
V
out
, is regulated with a reference current (I
ref
= 203 mA
typical) as shown in Figure 31.
Figure 31. Regulation Block
V
reg
I
ref
I
ref
96% I
FB
1.05 V
When I
FB
is lower than 96% of I
ref
, the V
reg
which is the
output of the regulation block is as high as V
control(max)
(1.05 V typical ) that gives the maxi mum value on V
ton
.As
a result, it gives the maximum MOSFET on time and V
out
increases. When I
FB
is higher than I
ref
, the V
reg
becomes 0
V that gives no MOSFET on time and V
out
decreases. As
a re sult, the output voltage V
out
is regulated around t he
range between 96% and 100% of the nomi nal value of R
FB
I
ref
.
Based on (eq.8) for a particular power level, the V
control
is inversely proportional to V
ac
2
. Hence, in high V
ac
condition V
control
is lower. It means that I
FB
or output
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NCP1601BDR2G

Mfr. #:
Buy NCP1601BDR2G
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC Fixed Frequency DCM/CRM PFC
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