RMLV1616A Series
R10DS0258EJ0100 Rev.1.00 Page 7 of 14
2016.01.06
Write Cycle
Parameter Symbol Min. Max. Unit Note
Write cycle time t
WC
55 ─ ns
Address valid to write end t
AW
35 ─ ns
Chip select to write end t
CW
35 ─ ns
Write pulse width t
WP
35 ─ ns 16
LB#,UB# valid to write end t
BW
35 ─ ns
Address setup time to write start t
AS
0 ─ ns
Write recovery time from write end t
WR
0 ─ ns
Data to write time overlap t
DW
25 ─ ns
Data hold from write end t
DH
0 ─ ns
Output enable from write end t
OW
5 ─ ns 17
Output disable to output in high-Z t
OHZ
0 18 ns 17,18
Write to output in high-Z t
WHZ
0 18 ns 17,18
Note 16. t
WP
is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
17. This parameter is sampled and not 100% tested.
18. t
OHZ
and t
WHZ
are defined as the time when the DQ pins enter a high-impedance state and are not referred to
the DQ levels.
BYTE# Timing Conditions (BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types)
Parameter Symbol Min. Max. Unit Note
Byte setup time t
BS
5 - ms
Byte recovery time t
BR
5 - ms
BYTE# Timing Waveforms
CS2
BYTE#
t
BS
t
BR
CS1#
