LOW SKEW 1 TO 4 CLOCK BUFFER
MDS 651 C 2 Revision 120805
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS651
Pin Assignment
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01
µF should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible.
A 33
Ω series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS651 is capable of, careful attention must be paid to board
layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30
Ω series termination
on one output (with 33
Ω on the others) will cause at least 15 ps of skew.
1
2
3
4
5
6
7
8
ICLK
Q1
Q2
Q3
Q4
OE
VDD
GND
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 ICLK Input Clock Input. 3.3 V tolerant input.
2 Q1 Output Clock Output 1.
3 Q2 Output Clock Output 2.
4 Q3 Output Clock Output 3.
5 Q4 Output Clock Output 4.
6 GND Power Connect to ground.
7 VDD Power Connect to +1.8 V or +2.5 V.
8 OE Input Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
