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XC9572-15TQ100I

P1-P3P4-P6P7-P9
XC9572 In-System Programmable CPLD
4 www.xilinx.com DS065 (v4.3) April 3, 2006
Product Specification
R
AC Characteristics
Symbol Parameter
XC9572-7 XC9572-10 XC9572-15
UnitsMin Max Min Max Min Max
T
PD
I/O to output valid - 7.5 - 10.0 - 15.0 ns
T
SU
I/O setup time before GCK 4.5 - 6.0 - 8.0 - ns
T
H
I/O hold time after GCK 0 - 0 - 0 - ns
T
CO
GCK to output valid - 4.5 - 6.0 - 8.0 ns
f
CNT
(1)
16-bit counter frequency 125.0 - 111.1 - 95.2 - MHz
f
SYSTEM
(2)
Multiple FB internal operating frequency 83.3 - 66.7 - 55.6 - MHz
T
PSU
I/O setup time before p-term clock input 0.5 - 2.0 - 4.0 - ns
T
PH
I/O hold time after p-term clock input 4.0 - 4.0 - 4.0 - ns
T
PCO
P-term clock output valid - 8.5 - 10.0 - 12.0 ns
T
OE
GTS to output valid - 5.5 - 6.0 - 11.0 ns
T
OD
GTS to output disable - 5.5 - 6.0 - 11.0 ns
T
POE
Product term OE to output enabled - 9.5 - 10.0 - 14.0 ns
T
POD
Product term OE to output disabled - 9.5 - 10.0 - 14.0 ns
T
WLH
GCK pulse width (High or Low) 4.0 - 4.5 - 5.5 - ns
T
APRPW
Asynchronous preset/reset pulse width (High
or Low)
7.0 - 7.5 - 8.0 - ns
Notes:
1. f
CNT
is the fastest 16-bit counter frequency available, using the local feedback when applicable.
f
CNT
is also the Export Control Maximum flip-flop toggle rate, f
TOG
.
2. f
SYSTEM
is the internal operating frequency for general purpose system designs spanning multiple FBs.
Figure 3:
AC Load Circuit
Device Output
Output Type V
TEST
5.0V
3.3V
V
TEST
R
1
160Ω
260Ω
R
1
R
2
C
L
R
2
120Ω
360Ω
C
L
35 pF
35 pF
DS067_03_110101
V
CCIO
5.0V
3.3V
XC9572 In-System Programmable CPLD
DS065 (v4.3) April 3, 2006 www.xilinx.com 5
Product Specification
R
Internal Timing Parameters
Symbol Parameter
XC9572-7 XC9572-10 XC9572-15
UnitsMinMaxMinMaxMinMax
Buffer Delays
T
IN
Input buffer delay - 2.5 - 3.5 - 4.5 ns
T
GCK
GCK buffer delay - 1.5 - 2.5 - 3.0 ns
T
GSR
GSR buffer delay - 4.5 - 6.0 - 7.5 ns
T
GTS
GTS buffer delay - 5.5 - 6.0 - 11.0 ns
T
OUT
Output buffer delay - 2.5 - 3.0 - 4.5 ns
T
EN
Output buffer enable/disable delay - 0 - 0 - 0 ns
Product Term Control Delays
T
PTCK
Product term clock delay - 3.0 - 3.0 - 2.5 ns
T
PTSR
Product term set/reset delay - 2.0 - 2.5 - 3.0 ns
T
PTTS
Product term 3-state delay - 4.5 - 3.5 - 5.0 ns
Internal Register and Combinatorial Delays
T
PDI
Combinatorial logic propagation delay - 0.5 - 1.0 - 3.0 ns
T
SUI
Register setup time 1.5 - 2.5 - 3.5 - ns
T
HI
Register hold time 3.0 - 3.5 - 4.5 - ns
T
COI
Register clock to output valid time - 0.5 - 0.5 - 0.5 ns
T
AOI
Register async. S/R to output delay - 6.5 - 7.0 - 8.0 ns
T
RAI
Register async. S/R recover before clock 7.5 - 10.0 - 10.0 - ns
T
LOGI
Internal logic delay - 2.0 - 2.5 - 3.0 ns
T
LOGILP
Internal low power logic delay - 10.0 - 11.0 - 11.5 ns
Feedback Delays
T
F
FastCONNECT feedback delay - 8.0 - 9.5 - 11.0 ns
T
LF
Function block local feedback delay - 4.0 - 3.5 - 3.5 ns
Time Adders
T
PTA
(1)
Incremental product term allocator delay - 1.0 - 1.0 - 1.0 ns
T
SLEW
Slew-rate limited delay - 4.0 - 4.5 - 5.0 ns
Notes:
1. T
PTA
is multiplied by the span of the function as defined in the XC9500 family data sheet.
XC9572 In-System Programmable CPLD
6 www.xilinx.com DS065 (v4.3) April 3, 2006
Product Specification
R
XC9572 I/O Pins
Function
Block
Macro-
cell
PC44 PC84 PQ100 TQ100
BScan
Order
Function
Block
Macro-
cell
PC44 PC84 PQ100 TQ100
BScan
Order
1 1 – 4 18 16 213 3 1 – 25 43 41 105
1 2 1 1 15 13 210 3 2 11 17 34 32 102
1 3 – 6 20 18 207 3 3 – 31 51 49 99
1 4 – 7 22 20 204 3 4 – 32 52 50 96
1 5 2 2 16 14 201 3 5 12 19 37 35 93
1 6 3 3 17 15 198 3 6 – 34 55 53 90
1 7 – 11 27 25 195 3 7 – 35 56 54 87
1 8 4 5 19 17 192 3 8 13 21 39 37 84
1 9 5
[1]
9
[1]
24
[1]
22
[1]
189 3 9 14 26 44 42 81
1 10 – 13 30 28 186 3 10 – 40 62 60 78
1 11 6
[1]
10
[1]
25
[1]
23
[1]
183 3 11 18 33 54 52 75
1 12 – 18 35 33 180 3 12 – 41 63 61 72
1 13 – 20 38 36 177 3 13 – 43 65 63 69
1 14 7
[1]
12
[1]
29
[1]
27
[1]
174 3 14 19 36 57 55 66
1 15 8 14 31 29 171 3 15 20 37 58 56 63
1 16 – 23 41 39 168 3 16 – 45 67 65 60
1 17 9 15 32 30 165 3 17 22 39 60 58 57
1 18 – 24 42 40 162
318––615954
2 1 – 63 89 87 159 4 1 – 46 68 66 51
2 2 35 69 96 94 156 4 2 24 44 66 64 48
2 3 – 67 93 91 153 4 3 – 51 73 71 45
2 4 – 68 95 93 150 4 4 – 52 74 72 42
2 5 36 70 97 95 147 4 5 25 47 69 67 39
2 6 37 71 98 96 144 4 6 – 54 78 76 36
2 7 – 76
[2]
5
[2]
3
[2]
141 4 7 – 55 79 77 33
2 8 38 72 99 97 138 4 8 26 48 70 68 30
2 9 39
[1]
74
[1]
1
[1]
99
[1]
135 4 9 27 50 72 70 27
2 10 – 75 3 1 132 4 10 – 57 83 81 24
2 11 40
[1]
77
[1]
6
[1]
4
[1]
129 4 11 28 53 76 74 21
2 12 – 79 8 6 126 4 12 – 58 84 82 18
2 13 – 80 10 8 123 4 13 – 61 87 85 15
2 14 42
[3]
81
[3]
11
[3]
9
[3]
120 4 14 29 56 80 78 12
2 15 43 83 13 11 117 4 15 33 65 91 89 9
2 16 – 82 12 10 114 4 16 – 62 88 86 6
2 17 44 84 14 12 111 4 17 34 66 92 90 3
2 18 – – 94 92 108
418––81790
Notes:
1. Global control piN.
2. Global control pin GTS1 for PC84, PQ100, and TQ100.
3. Global control pin GTS1 for PC44.
P1-P3P4-P6P7-P9

XC9572-15TQ100I

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