REV. C
ADM1025/ADM1025A
–10–
TEMPERATURE MEASUREMENT SYSTEM
Internal Temperature Measurement
The ADM1025/ADM1025A contains an on-chip band gap
temperature sensor whose output is digitized by the on-chip
ADC. The temperature data is stored in the Local Temperature
Value Register (Address 27h). As both positive and negative
temperatures can be measured, the temperature data is stored in
twos complement format, as shown in Table III. Theoretically, the
temperature sensor and ADC can measure temperatures
from –128°C to +127°C with a resolution of 1°C, although
temperatures below 0°C and above +100°C are outside the
operating temperature range of the device.
External Temperature Measurement
The ADM1025/ADM1025A can measure temperature using an
external diode sensor or diode-connected transistor connected to
Pins 9 and 10.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute
value of V
BE
, varies from device to device, and individual calibration
is required to null this out, so the technique is unsuitable for
mass production.
The technique used in the ADM1025/ADM1025A is to measure
the change in V
BE
when the device is operated at two differ-
ent currents. This is given by:
VKTqIn N
BE
()
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvins.
N is the ratio of the two currents.
Figure 4 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor provided for tem-
perature monitoring on some microprocessors, but it could
equally well be a discrete transistor.
If a discrete transistor is used, the collector will not be grounded
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+ input.
If an NPN transistor is used, the emitter is connected to the
D– input and the base to the D+ input.
Bit 6 of Status Register 2 (42h) is set if a remote diode fault is
detected. The ADM1025/ADM1025A detects shorts from D+
to GND or supply, as well as shorts/opens between D+/D–.
LOW-PASS
FILTER
f
C
= 65kHz
BIAS
DIODE
REMOTE
SENSING
TRANSISTOR
IN II
BIAS
D+
D–
V
OUT+
V
OUT–
TO
ADC
V
DD
Figure 4. Signal Conditioning for External Diode
Temperature Sensors
Table III. Temperature Data Format
Temperature Digital Output
–128°C 1000 0000
–125°C 1000 0011
–100°C 1001 1100
–75°C 1011 0101
–50°C 1100 1110
–25°C 1110 0111
0°C 0000 0000
+10°C 0000 1010
+25°C 0001 1001
+50°C 0011 0010
+75°C 0100 1011
+100°C 0110 0100
+125°C 0111 1101
+127°C 0111 1111
To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to ground
but is biased above ground by an internal diode at the D– input.
If the sensor is used in a very noisy environment, a capacitor of
value up to 1 nF may be placed between the D+ and D– inputs
to filter the noise.
To measure V
BE
, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed through
a 65 kHz low-pass filter to remove noise, then to a chopper-
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage
proportional to V
BE
. This voltage is measured by the ADC to
give a temperature output in 8-bit twos complement format. To
further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles. An external
temperature measurement takes nominally 34.8 ms.
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments and care
must be taken to protect the analog inputs from noise, particularly
when measuring the very small voltages from a remote diode
sensor. The following precautions should be taken:
1. Place the ADM1025/ADM1025A as close as possible to the
remote sensing diode. Provided that the worst noise sources,
such as clock generators, data/address buses, and CRTs, are
avoided, this distance can be four to eight inches.
2. Route the D+ and D– tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground plane
under the tracks if possible.
3. Use wide tracks to minimize inductance and reduce noise
pickup. 10 mil track minimum width and spacing is
recommended.
10MIL
10MIL
10MIL
10MIL
10MIL
10MIL
10MIL
GND
D+
D–
GND
Figure 5. Arrangement of Signal Tracks
REV. C
ADM1025/ADM1025A
–11–
4. Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder joints
are used, make sure that they are in both the D+ and D–
path and at the same temperature.
Thermocouple effects should not be a major problem as 1°C
corresponds to about 240 µV, and thermocouple voltages are
about 3 µV/
o
C of temperature difference. Unless there are two
thermocouples with a big temperature differential between
them, thermocouple voltages should be much less than 200 µV.
5. Place 0.1 µF bypass and 1 nF input filter capacitors close to
the ADM1025/ADM1025A.
6. If the distance to the remote sensor is more than eight inches,
the use of twisted pair cable is recommended. This will work
up to about 6 to 12 feet.
7. For really long distances (up to 100 feet) use shielded twisted
pair, such as Belden #8451 microphone cable. Connect the
twisted pair to D+ and D– and the shield to GND close to
the ADM1025/ADM1025A. Leave the remote end of the
shield unconnected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor may
be reduced or removed.
Cable resistance can also introduce errors. 1 series resistance
introduces about 0.5°C error.
LIMIT VALUES
High and low limit values for each measurement channel are
stored in the appropriate limit registers. As each channel is
measured, the measured value is stored and compared with the
programmed limit.
STATUS REGISTERS
The results of limit comparisons are stored in Status Registers 1
and 2. The Status Register bit for a particular measurement
channel reflects the status of the last measurement and limit
comparison on that channel. If a measurement is within limits,
the corresponding Status Register bit will be cleared to “0.” If the
measurement is out of limits, the corresponding status register
bit will be set to “1.”
The state of the various measurement channels may be polled
by reading the Status Registers over the serial bus. Reading the
Status Registers does not affect their contents. Out-of-limit
temperature/voltage events may also be used to generate an
interrupt so that remedial action, such as turning on a cooling
fan, may be taken immediately. This is described in the section
on RST and INT.
MONITORING CYCLE TIME
The monitoring cycle begins when a 1 is written to the Start Bit
(Bit 0) of the Configuration Register. The ADC measures each
analog input in turn and as each measurement is completed the
result is automatically stored in the appropriate value register. This
“round-robin” monitoring cycle continues until it is disabled by
writing a 0 to Bit 0 of the Configuration Register.
As the ADC will normally be left to free-run in this manner, the
time taken to monitor all the analog inputs will normally not be
of interest, since the most recently measured value of any input
can be read out at any time.
INPUT SAFETY
Scaling of the analog inputs is performed on-chip, so external
attenuators are normally not required. However, since the power
supply voltages will appear directly at the pins, it is advisable to
add small external resistors in series with the supply traces to the
chip to prevent damaging the traces or power supplies should
an accidental short such as a probe connect two power
supplies together.
As the resistors will form part of the input attenuators, they will
affect the accuracy of the analog measurement if their value is
too high. The analog input channels are calibrated assuming an
external series resistor of 500 , and the accuracy will remain
within specification for any value from zero to 1 k, so a standard
510 resistor is suitable.
The worst such accident would be connecting 0 V to 12 V—a
total of 12 V difference. With the series resistors, this would draw
a maximum current of approximately 12 mA.
LAYOUT AND GROUNDING
Analog inputs will provide best accuracy when referred to a clean
ground. A separate, low impedance ground plane for analog
ground, which provides a ground point for the voltage dividers
and analog components, will provide best performance but is
not mandatory.
The power supply bypass, the parallel combination of 10 µF
(electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors
connected between Pin 9 and ground, should also be located as
close as possible to the ADM1025/ADM1025A.
RST/INT OUTPUT
As previously mentioned, Pin 16 is a multifunction pin. Its state
after power-on is latched to set the lowest two bits of the serial bus
address. During NAND tree board-level connectivity testing, it
functions as the output of the NAND tree. It may also be used
as a reset output, or as an interrupt output for out-of-limit
temperature/voltage events.
Pin 16 is programmed as a reset output by clearing Bit 0 of the
Test Register and setting Bit 7 of the VID Register. A low going,
20 ms, reset output pulse can then be generated by setting Bit 4
of the Configuration Register.
If Bit 7 of the VID Register is cleared, Pin 16 can be programmed
as an interrupt output for out-of-limit temperature/voltage events
(INT). Desired interrupt operation is achieved by changing the
values of Bits 1 and 0 of the Test Register as shown in Table IV.
Note, however, that Bits 2 to 7 of the Test Register must be
zeros (not don’t cares). If, for example, INT is programmed for
thermal and voltage interrupts, then if any temperature or voltage
measurement goes outside its respective high or low limit, the
INT output will go low. It will remain low until Status Register 1
is read, when it will be cleared. If the temperature or voltage
remains out of limit, INT will be reasserted on the next monitoring
cycle. INT can also be cleared by issuing an Alert Response
Address Call.
REV. C
ADM1025/ADM1025A
–12–
Table IV. Controlling the Operation of INT
Test Register
Bit 1 Bit 0 Function
00Interrupts Disabled
01Thermal Interrupt Only
10Voltage Interrupt Only
11Voltage and Thermal Interrupts
Note that Bit 7 of VID register should be zero, and that Bits 2 to 7 of Test
Register must be zeros.
When Pin 16 is used as a RST or INT output, it is open-drain and
requires an external pull-up resistor. This will restrict the address
function on Pin 16 to being high at power-up. If the RST or INT
function is required and two ADM1025/ADM1025As are to be
used on the same serial bus, A1/A0 can be set to 10 by using a
high value pull-up on Pin 16 (100 k or greater). This will not
override the “floating” condition of ADD during power-up.
Note, however, that the RST/INT outputs of two or more
devices cannot be wire-OR’d, since the devices would then have
the same address. If the RST/INT outputs need to be connected
to a common interrupt line, they can be OR’d together using the
circuit of Figure 6.
If the RST or INT functionality is not required, a third address
may be used by setting A1/A0 to 00 by using a 1 k pull-down
resistor on Pin 16. Note that this address should not be used if
RST or INT is required, since using this address will cause the
device to appear to be generating resets or interrupts, since Pin 16
will be permanently tied low.
A1/A0 = 10
ADD/RST/INT/NTO
SDA
SCL
ADM1025/
ADM1025A
No. 2
R2
470k
V
CC
A1/A0 = 01
R1
1k
V
CC
R5
4.7k
V
CC
RST OR INT
OPEN-COLLECTOR
AND GATE
ADD/RST/INT/NTO
SDA
SCL
ADM1025/
ADM1025A
No. 1
Figure 6. Using Two ADM1025/ADM1025As on the Same
Bus with a Common Interrupt
GENERATING AN SMBALERT
The INT output can be used as an interrupt output or can be used
as an SMBALERT. One or more INT outputs can be connected
to a common SMBALERT line connected to the master. If a
device’s INT line goes low, the following procedure occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the Alert
Response Address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3. The device whose INT output is low responds to the Alert
Response Address, and the master reads its device address.
The address of the device is now known and it can be
interrogated in the usual way.
4. If more than one device’s INT output is low, the one with
the lowest device address will have priority, in accordance
with normal SMBus arbitration.
5. Once the ADM1025/ADM1025A has responded to the Alert
Response Address, it will reset its INT output; however, if
the error condition that caused the interrupt persists, INT
will be reasserted on the next monitoring cycle.
NAND TREE TESTS
A NAND tree is provided in the ADM1025/ADM1025A for
Automated Test Equipment (ATE) board level connectivity
testing. The device is placed into NAND Test Mode by power-
ing up with Pin 9 (D-/NTI) held high. This pin is automatically
sampled after power-up, and if it is connected high, the NAND
test mode is invoked.
In NAND test mode, all digital inputs may be tested as illus-
trated below. ADD/RST/INT/NTO will become the NAND test
output pin.
To perform a NAND tree test, all pins are initially driven low.
The test vectors set all inputs low, then one-by-one toggle them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the out-
put of the tree, cycling toward the farthest, causes the output of
the tree to toggle with each input change. Allow for a typical
propagation delay of 500 ns. The structure of the NAND tree is
shown in Figure 7.
ADD/RST/INT/NTO
SDA
SCL
VID0
VID1
VID2
VID3
Figure 7. NAND Tree
Note: If any of the inputs shown in Figure 7 are unused, they
should not be connected directly to ground but via a resistor
such as 10 k. This will allow the ATE to drive every input high
so that the NAND tree test can be properly carried out. Refer to
Table XVI for Test Vectors.

ADM1025ARQ-REEL

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC MONITOR SYS/VOLT 5CH 16QSOP
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