84314AY www.icst.com/products/hiperclocks.html REV. C JANUARY 27, 2005
12
Integrated
Circuit
Systems, Inc.
ICS84314
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
CCA
shares the same power supply with V
CC
, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
CCA
as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
• Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
• Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination schemes can also be used but are not
shown in this example.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 25 (XTAL1) and 26 (XTAL2). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84314
VIA
X1
U1
R7
VCCA
C5
C1
VCC
C4
C16
GND
C3
PIN 1
C2
C11
