MC34025, MC33025
http://onsemi.com
8
OPERATING DESCRIPTION
The MC33025 and MC34025 series are high speed, fixed
frequency, double−ended pulse width modulator controllers
optimized for high frequency operation. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
solution with minimal external components. A
representative block diagram is shown in Figure 19.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components R
T
and C
T
. The R
T
pin
is set to a temperature compensated 3.0 V. By selecting the
value of R
T
, the charge current is set through a current mirror
for the timing capacitor C
T
. This charge current runs
continuously through C
T
. The discharge current ratio is to be
10 times the charge current, which yields the maximum duty
cycle of 90%. C
T
is charged to 2.8 V and discharged to 1.0
V. During the discharge of C
T
, the oscillator generates an
internal blanking pulse that resets the PWM Latch, inhibits
the outputs, and toggles the steering flip−flop. The threshold
voltages on the oscillator comparator is trimmed to
guarantee an oscillator accuracy of 5.0% at 25°C.
Additional dead time can be added by externally
increasing the charge current to C
T
as shown in Figure 24.
This changes the charge to discharge ratio of C
T
which is set
internally to I
charge
/10 I
charge
. The new charge to discharge
ratio will be:
% Deadtime +
I
additiona
l
) I
charge
10 (I
charge
)
A bidirectional clock pin is provided for synchronization
or for master/slave operation. As a master, the clock pin
provides a positive output pulse during the discharge of C
T
.
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge C
T
.
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 30 and 31 provide suggested
synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It
features a typical DC voltage gain of 95 dB and a gain
bandwidth product of 8.3 MHz with 75 degrees of phase
margin (Figure 4). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
have a Common Mode Voltage (V
CM
) input range of 1.5 V
to 5.5 V. The Error Amplifier Output is provided for external
loop compensation.
Soft−Start Latch
Soft−Start is accomplished in conjunction with an
external capacitor. The soft start capacitor is charged by an
internal 9.0 mA current source. This capacitor clamps the
output of the error amplifier to less than its normal output
voltage, thus limiting the duty cycle.
The time it takes for a capacitor to reach full charge is
given by:
t [ (4.5 • 10
5
)C
Soft-Start
A Soft−Start latch is incorporated to prevent erratic
operation of this circuitry. Two conditions can cause the
Soft−Start circuit to latch so that the Soft−Start capacitor
stays discharged. The first condition is activation of an
undervoltage lockout of either V
CC
or V
ref
. The second
condition is when current sense input exceeds 1.4 V. Since
this latch is “set dominant”, it cannot be reset until either of
these signals is removed, and the voltage at C
Soft−Start
is less
than 0.5 V.
PWM Comparator and Latch
A PWM circuit typically compares an error voltage with
a ramp signal. The outcome of this comparison determines
the state of the output. In voltage mode operation the ramp
signal is the voltage ramp of the timing capacitor. In current
mode operation the ramp signal is the voltage ramp induced
in a current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25 V offset such that whenever the
voltage at this pin exceeds the Error Amplifier Output
voltage minus 1.25 V, the PWM comparator will cause the
PWM latch to set, disabling the outputs. Once the PWM
latch is set, only a blanking pulse by the oscillator can reset
it, thus initiating the next cycle.
A toggle flip flop connected to the output of the PWM
latch controls which output is active. The flip flop is pulsed
by an OR gate that gets its inputs from the oscillator clock
and the output of the PWM latch. A pulse from either one
will cause the flip flop to enable the other output.
Current Limiting and Shutdown
A pin is provided to perform current limiting and
shutdown operations. Two comparators are connected to the
input of this pin. When the voltage at this pin exceeds 1.0 V,
one of the comparators is activated. The output of this
comparator sets the PWM latch, which disables the output.
In this way cycle−by−cycle current limiting is
accomplished. If a current limit resistor is used in series with
the power devices, the value of the resistor is found by:
R
Sense
+
1.0 V
I
pk (switch)
