160 dB Range 100 pA to 10 mA
Low Cost Logarithmic Converter
Data Sheet
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FEATURES
Optimized for fiber optic photodiode interfacing
8 full decades of range
Law conformance: 0.1 dB from 1 nA to 1 mA
Single-supply operation: 3.0 V to 5.5 V
Complete and temperature stable
Accurate laser trimmed scaling
Logarithmic slope of 10 mV/dB (at the VLOG pin)
Basic logarithmic intercept at 100 pA
Easy adjustment of slope and intercept
Output bandwidth of 10 MHz, 15 V/µs slew rate
Miniature 16-lead package (LFCSP)
Low power: ~4.5 mA quiescent current (enabled)
APPLICATIONS
High accuracy optical power measurement
Wide range baseband log compression
Versatile detector for APC loops
SIMPLIFIED BLOCK DIAGRAM
PDB
BIAS
VREF
I
PD
VPDB
VSUM
INPT
VSUM
GND GND
VPS2 PWDN VPS1
VREF
VLOG
BFIN
BFNG
VOUT
0.5V
ADL5303
~10kΩ
5kΩ
5
2
3
4
15
14
ACOM
7 11
10
16
12
6
8
9
13
10661-001
TEMPERATURE
COMPENSATION
Figure 1.
GENERAL DESCRIPTION
The ADL5303 is a monolithic logarithmic detector optimized
for the measurement of low frequency signal power in fiber
optic systems and offers a large dynamic range in a versatile and
easily used form. Wide measurement range and accuracy are
achieved using proprietary design and precise laser trimming.
The ADL5303 requires only a single positive supply, V
PS
, of 5 V.
When using low supply voltages, the log slope can be altered to
fit the available span. Low quiescent current and chip disable
facilitate use in battery-operated applications.
The input current, I
PD
, flows in the collector of an optimally
scaled NPN transistor, connected in a feedback path around a
low offset JFET amplifier. The current summing input node
operates at a constant voltage, independent of current, with
a default value of 0.5 V; this may be adjusted over a wide range.
An adaptive biasing scheme is provided for reducing photo-
diode dark current at very low light input levels. The VPDB pin
applies approximately 0.1 V reverse bias across the photodiode
for I
PD
= 100 pA, rising linearly to 2.0 V of reverse bias at I
PD
=
10 mA to improve response time at higher power levels. The
input pin INPT is flanked by the VSUM guard pins that track
the voltage at the summing node. Connecting the exposed pad
of the device to the VSUM pins provides a continuous guard to
minimize leakage into the INPT pin.
The default value of the logarithmic slope at the VLOG output
is set by an internal 5 kΩ resistor. Logarithmic slope can be
lowered with an external shunt resistor or increased using the
buffer and a pair of external feedback resistors. The addition of
a capacitor at the VLOG pin provides a simple low-pass filter.
The intermediate voltage, V
LOG
, is buffered in an output stage
that can swing to within about 100 mV of ground and the posi-
tive supply, V
PS
, and provides a peak current drive capacity of
±20 mA. An on-board 2 V reference is provided to facilitate
the repositioning of the intercept. The incremental bandwidth
of a translinear logarithmic amplifier inherently diminishes
for small input currents. At I
PD
=1 nA, the bandwidth of the
ADL5303 is approximately 2 kHz increasing in proportion to
I
PD
up to a maximum value of 10 MHz.
