IR3720
DATA SHEET
Page 6 of 20 www.irf.com 09/09/08
IC PIN FUNCTIONS
VDD PIN
This pin provides operational bias current to circuits
internal to the IR3720. Bypass it with a high quality
ceramic capacitor to the GND pin.
GND PIN
This pin returns operational bias current to its source.
It is also the reference to which the voltage VO is
measured, and it sinks the reference current
established by the external resistor R
T
.
VO PIN
Connect this pin to the location in the circuit where
voltage for the power calculation is desired to be
monitored. Since it also measures DCR voltage drop
it is critical that it be Kelvin connected to the buck
inductor output. Power accuracy may be degraded if
the voltage at this pin is below VO
min
.
VCS PIN
The average current into this pin is used to calculate
power. A switched current source internal to the
IR3720 will maintain the average voltage of this pin
equal to the voltage of the VO pin.
VREF FUNCTION
A voltage reference internal to the IR3720 drives the
V
REF
pin while the pin current is monitored and used
to set the amplitude of the current monitor switched
current source I
REF
. This pin should be connected to
GND through a precision resistor network R
T
. This
network may include provision for canceling the
positive temperature coefficient of the buck inductor’s
DC resistance (DCR).
ALERT# FUNCTION
The ALERT# pin is a multi-use pin. During normal
use it can be configured via the I
2
C as an open drain
ALERT# pin that will be driven logic low when new
data is available in the output register. After the
output register has been read via the I
2
C the ALERT#
will be released to its high resistance state. This pin
can also be programmed to pull low when the output
exceeds the programmable level.
ADDR PIN
The ADDR pin is an input that establishes the I
2
C
address. Valid addresses are selected by grounding,
floating, or wiring to VDD the ADDR pin. Table 1,
“User Selectable Addresses”, provides a mapping of
possible selections.
Table 1 User selectable addresses
ADDR pin configuration I
2
C Address
Low b’1110 000
Open b’1110 010
High b’1110 110
EXTCLK
This pin is a Schmitt trigger input for an optional
externally provided square wave clock. The duty ratio
of this externally provided clock, if used, shall be
between 40% and 60%. If no external clock is used,
connect this pin to GND and the internal clock will be
used.
SCL
SCL is the I
2
C clock and is capable of functioning
with a rate as low as 10 kHz. It will continue to
function as the rate is increased to 400 kHz. This
device is considered a slave, and therefore uses the
SCL as an input only.
SDA
SDA is monitored as data input during master to
slave transactions, and is driven as data output
during slave to master transactions as indicated in
the Packet Protocol section to follow.
