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CS5530-ISZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
CS5530
DS742F3 7
5 V DIGITAL CHARACTERISTICS
(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 11.)
3 V DIGITAL CHARACTERISTICS
(T
A
= 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 11.)
11. All measurements performed under static conditions.
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except SCLK
SCLK
V
IH
0.6 VD+
(VD+) - 0.45
-
-
VD+
VD+
V
Low-Level Input Voltage All Pins Except SCLK
SCLK
V
IL
0.0
0.0
-0.8
0.6
V
High-Level Output Voltage A0 and A1, I
out
= -1.0 mA
SDO, I
out
= -5.0 mA
V
OH
(VA+) - 1.0
(VD+) - 1.0
--V
Low-Level Output Voltage A0 and A1, I
out
= 1.0 mA
SDO, I
out
= 5.0 mA
V
OL
- - (VA-) + 0.4
0.4
V
Input Leakage Current I
in
-±1±10µA
SDO 3-State Leakage Current I
OZ
--±10µA
Digital Output Pin Capacitance C
out
-9-pF
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage All Pins Except SCLK
SCLK
V
IH
0.6 VD+
(VD+) - 0.45
-VD+
VD+
V
Low-Level Input Voltage All Pins Except SCLK
SCLK
V
IL
0.0
0.0
-0.8
0.6
V
High-Level Output Voltage A0 and A1, I
out
= -1.0 mA
SDO, I
out
= -5.0 mA
V
OH
(VA+) - 1.0
(VD+) - 1.0
-- V
Low-Level Output Voltage A0 and A1, I
out
= 1.0 mA
SDO, I
out
= 5.0 mA
V
OL
- - (VA-) + 0.4
0.4
V
Input Leakage Current I
in
-±1±10µA
SDO 3-State Leakage Current I
OZ
--±10µA
Digital Output Pin Capacitance C
out
-9-pF
CS5530
8 DS742F3
DYNAMIC CHARACTERISTICS
12. The ADCs use a Sinc
5
filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc
5
filter
followed by a Sinc
3
filter for the other OWRs. OWR
sinc5
refers to the 3200 Sps (FRS = 1) or 3840 Sps
(FRS = 0) word rate associated with the Sinc
5
filter.
13. The single conversion mode only outputs fully settled conversions. See Table 1 for more details about
single conversion mode timing. OWR
SC
is used here to designate the different conversion time
associated with single conversions.
14. The continuous conversion mode outputs every conversion. This means that the filter’s settling time
with a full-scale step input in the continuous conversion mode is dictated by the OWR.
ABSOLUTE MAXIMUM RATINGS
(DGND = 0 V; See Note 15.)
Notes: 15. All voltages with respect to ground.
16. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.
17. VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.
18. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.
19. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ±50 mA.
20. Total power dissipation, including all input currents and output currents.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter Symbol Ratio Unit
Modulator Sampling Rate f
s
MCLK/16 Sps
Filter Settling Time to 1/2 LSB (full-scale Step Input)
Single Conversion mode (Notes 12, 13, and 14)
Continuous Conversion mode, OWR < 3200 Sps
Continuous Conversion mode, OWR ≥ 3200 Sps
t
s
t
s
t
s
1/OWR
SC
5/OWR
sinc5
+ 3/OWR
5/OWR
s
s
s
Parameter Symbol Min Typ Max Unit
DC Power Supplies (Notes 16 and 17)
Positive Digital
Positive Analog
Negative Analog
VD+
VA+
VA-
-0.3
-0.3
+0.3
-
-
-
+6.0
+6.0
-3.75
V
V
V
Input Current, Any Pin Except Supplies (Notes 18 and 19) I
IN
--±10mA
Output Current I
OUT
--±25mA
Power Dissipation (Note 20) PDN - - 500 mW
Analog Input Voltage VREF pins
AIN Pins
V
INR
V
INA
(VA-) -0.3
(VA-) -0.3
-
-
(VA+) + 0.3
(VA+) + 0.3
V
V
Digital Input Voltage V
IND
-0.3 - (VD+) + 0.3 V
Ambient Operating Temperature T
A
-40 - 85 °C
Storage Temperature T
stg
-65 - 150 °C
CS5530
DS742F3 9
SWITCHING CHARACTERISTICS
(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0
V, Logic 1 = VD+; C
L
= 50 pF; See Figures 1 and 2.)
Notes: 21. Device parameters are specified with a 4.9152 MHz clock.
22. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
23. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
Parameter Symbol Min Typ Max Unit
Master Clock Frequency (Note 21)
External Clock or Crystal Oscillator
MCLK
1 4.9152 5 MHz
Master Clock Duty Cycle 40 - 60 %
Rise Times (Note 22)
Any Digital Input Except SCLK
SCLK
Any Digital Output
t
rise
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Fall Times (Note 22)
Any Digital Input Except SCLK
SCLK
Any Digital Output
t
fall
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Start-up
Oscillator Start-up Time XTAL = 4.9152 MHz (Note 23) t
ost
-20-ms
Serial Port Timing
Serial Clock Frequency SCLK 0 - 2 MHz
Serial Clock Pulse Width High
Pulse Width Low
t
1
t
2
250
250
-
-
-
-
ns
ns
SDI Write Timing
CS
Enable to Valid Latch Clock t
3
50 - - ns
Data Set-up Time prior to SCLK rising t
4
50 - - ns
Data Hold Time After SCLK Rising t
5
100 - - ns
SCLK Falling Prior to CS
Disable t
6
100 - - ns
SDO Read Timing
CS
to Data Valid t
7
--150ns
SCLK Falling to New Data Bit t
8
--150ns
CS
Rising to SDO Hi-Z t
9
--150ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

CS5530-ISZR

Mfr. #:
Buy CS5530-ISZR
Manufacturer:
Cirrus Logic
Description:
Analog to Digital Converters - ADC IC 24-Bit 1-ch Low Noise ADC
Lifecycle:
New from this manufacturer.
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