6
LTC1536
1536fa
PIN FUNCTIONS
UUU
V
CC3
(Pin 1): 3.3V Sense Input and Power Supply Pin for
the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor.
V
CC5
(Pin 2): 5V Sense Input. Used as gate drive for RST
output FET when the voltage on V
CC5
is greater than the
voltage on V
CC3
.
V
CCA
(Pin 3): 1V Sense, High Impedance Input. Can be
used as a logic input with a 1V threshold. If unused it can
be tied to either V
CC3
or V
CC5
.
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to V
CC3
, buffered compliment of RST.
An external pull-down on the RST pin will drive this pin high.
RST (Pin 6):
Reset Logic Output. Active low, open-drain
logic output with weak pull-up to V
CC3
. Can be pulled up
greater than V
CC3
when interfacing to 5V logic.
V
CC3
SOFT RESET
RESET
3V
CCA
2V
CC5
TO
POWER
DETECT
8PBR
7 SRST
4GND
REF
PBR
TIMER
200ms
RESET
GENERATOR
POWER
DETECT/
GATE DRIVE
V
CC3
6 RST
5
V
CC3
V
CC3
V
CC5
RST
6µA
V
CC3
7µA
6µA
–
+
FAST
+
–
FAST
+
–
SLOW
+
–
FAST
–
+
SLOW
+
–
SLOW
1V
CC3
TO POWER DETECT
AND V
CC
INTERNAL
1326 BD
BLOCK DIAGRAM
W
Asserted when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than two
seconds and for an additional 200ms after PBR is released.
SRST (Pin 7): “Soft” Reset. Active low, open-drain logic
output with weak pull-up to V
CC3
. Can be pulled up greater
than V
CC3
when interfacing to 5V logic. Asserted for 100µs
after PBR is held low for less than two seconds and released.
PBR (Pin 8): Pushbutton Reset. Active low logic input with
weak pull-up to V
CC3
. Can be pulled up greater than V
CC3
when interfacing to 5V logic. When asserted for less than
two seconds, outputs a soft reset 100µs pulse on the SRST
pin. When PBR is asserted for greater than two seconds,
the RST output is forced low and remains low until 200ms
after PBR is released.
