8
LTC1536
1536fa
When the PBR is pulled low for less than t
PB
(≈ 2 sec), a
narrow (100µs typ) soft reset pulse is generated on the
SRST output pin after the button is released. The push-
button circuitry contains an internal debounce counter
which delays the output of the soft reset pulse by typically
20ms. This pin can be OR-tied to the RST pin and issue
what is called a “soft” reset. The SRST thereby resets the
microprocessor without interrupting the DRAM refresh
cycle. In this manner DRAM information remains undis-
turbed. Alternatively, SRST may be monitored by the
processor to initiate a software-controlled reset.
When the PBR pin is held low for longer than t
PB
( ≈ 2 sec),
a standard reset is generated. Once the 2-second period
has elapsed, a reset signal is produced by the pushbutton
logic, thereby clearing the reset counter. Once the PBR
pin is released, the reset counter begins counting the
reset period (200ms nominal). Consequently, the reset
outputs remain asserted for approximately 200ms after
the button is released.
Fast Undervoltage for PCI Applications
The LTC1536 is designed for PCI Local Bus applications
that require reset to be asserted quickly in response to one
or both of the power supply rails (5V and 3.3V) going out
of spec. The spec for t
FAIL
and t
PF
are met with enough
margin to give the designer the ability to add follow-on
logic as needed by system requirements. The V
CCA
pin can
be used to monitor the “power good” signal and keep reset
applied until both supplies are in spec and the power good
signal is high.
Glitch Immunity and Fast Undervoltage Detection
The LTC1536 achieves its high speed characteristics while
maintaining glitch immunity by using two sets of com-
parators. The V
CC5
and V
CC3
sense inputs each have two
comparators set at different thresholds. A slow, very
accurate comparator monitors the supply for precision
undervoltage detection. In parallel, but with a threshold
250mV lower than the precision threshold, is a very fast
comparator that detects when the supply is quickly going
out of specification. Because the fast comparator thresh-
old is set 250mV above the PCI specification, typical
values for t
FAIL
can be negative.
3V or 5V Power Detect/Gate Drive
The LTC1536 for the most part is powered internally from
the V
CC3
pin. The exception is at the gate drive of the output
FET on the RST pin. On the gate to this FET is power detect
circuitry used to detect and drive the gate from either the
3.3V pin or the 5V pin, whichever pin has the highest
potential. This ensures the part pulls the RST pin low as
soon as either input pin is ≥ 1V.
Extended ESD Tolerance of the PBR Input Pin
The PBR pin is susceptible to ESD since it can be brought
out to a front panel in normal applications. The ESD
tolerance of this pin can be increased by adding a resistor
in series with the PBR pin. A 10k resistor can increase the
ESD tolerance of the PBR pin to approximately 10kV. The
PBR’s internal pull-up current of 7µA typical means there
is only 70mV (150mV max) dropped across the resistor.
APPLICATIONS INFORMATION
WUU
U
TYPICAL APPLICATIONS N
U
1
2
3
4
8
7
6
5
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
LTC1536
PCI
LOCAL
BUS
0.1µF
3.3V SUPPLY
RESET
5V SUPPLY
1536 TA08
0.1µF
ONBOARD
DEVICE
PCI Expansion Board RST Generation
Dual Supply Monitor (3.3V and 5V, V
CCA
Input
Monitoring “Power Good”)
1
2
3
4
8
7
6
5
V
CC3
V
CC5
V
CCA
GND
PBR
SRST
RST
RST
LTC1536
3.3V
SYSTEM RESET
5V
PWR GOOD
1536 TA04
