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GS9076-CNE3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
GS9076 Data Sheet
44617 - 1 January 2008 16 of 25
4. Detailed Description
The GS9076 is a SD-SDI Serial Digital Reclocker designed to automatically
recover the embedded clock from a digital video signal and re-time the incoming
video data.
The GS9076 will recover the embedded clock signal and re-time the data from a
SMPTE 259M-C compliant digital video signal.
Using the functional block diagram (page 2) as a guide, Slew Rate Phase Lock
Loop (S-PLL) on page 16 to Lock and LOS on page 20 describes each aspect of
the GS9076 in detail.
4.1 Slew Rate Phase Lock Loop (S-PLL)
The term “slew” refers to the output phase of the PLL in response to a step change
at the input. Linear PLLs have an output phase response characterized by an
exponential response whereas an S-PLL’s output is a ramp response (see
Figure 4-1). Because of this non-linear response characteristic, traditional small
signal analysis is not possible with an S-PLL.
Figure 4-1: PLL Characteristics
0.2
0.1
0.0
INPUT
OUTPUT
SLEW PLL RESPONSE
PHASE (UI)
0.2
0.1
0.0
INPUT
OUTPUT
LINEAR (CONVENTIONAL) PLL RESPONSE
PHASE (UI)
GS9076 Data Sheet
44617 - 1 January 2008 17 of 25
The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of
an S-PLL is independent of the transition density of the input data. Pseudo-random
data has a transition density of 0.5 verses a pathological signal which has a
transition density of 0.05. The loop bandwidth of a linear PLL will change
proportionally with this change in transition density. With an S-PLL, the loop
bandwidth is defined by the jitter at the data input. This translates to infinite loop
bandwidth with a zero jitter input signal. This allows the loop to correct for small
variations in the input jitter quickly, resulting in very low output jitter. The loop
bandwidth of the GS9076’s PLL is defined at 0.2UI of input jitter.
The PLL consists of two acquisition loops. First is the Frequency Acquisition (FA)
loop. This loop is active when the device is not locked and is used to achieve lock
to the supported data rates. Second is the phase acquisition (PA) loop. Once
locked, the PA loop tracks the incoming data and makes phased corrections to
produce a re-clocked output.
4.2 VCO
The internal VCO of the GS9076 is an LC oscillator. It is trimmed at the time of
manufacture to capture all data rates over temperature and operation voltage
ranges.
Integrated into the VCO is a series of programmable dividers used to achieve all
serial data rates, as well as additional dividers for the frequency acquisition loop.
4.3 Charge Pump
During frequency acquisition, the charge pump has two states, “pump-up” and
“pump-down,” which is produced by a leading or lagging phase difference between
the input and the VCO frequency.
During phase acquisition, there are two levels of “pump-up” and two levels of
“pump down” produced for leading and lagging phase difference between the input
and VCO frequency. This is to allow for greater precision of VCO control.
The charge pump produces these signals by holding the integrated frequency
information on the external loop-filter capacitor, C
LF
. The instantaneous frequency
information is the result of the current flowing through an internal resistor
connected to the loop-filter capacitor.
GS9076 Data Sheet
44617 - 1 January 2008 18 of 25
4.4 Frequency Acquisition Loop — The Phase-Frequency Detector
An external crystal of 14.140 MHz is used as a reference to keep the VCO centered
at the last known data rate. This allows the device to achieve a fast synchronous
lock, especially in cases where a known data rate is interrupted. The crystal
reference is also used to clock internal timers and counters. To keep the optimal
performance of the reclocker over all operating conditions, the crystal frequency
must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is
available from GENNUM.
The VCO is divided by a selected ratio which is dependant on the input data rate.
The resultant is then compared to the crystal frequency. If the divided VCO
frequency and the crystal frequency are within 1% of each other, the PLL is
considered to be locked to the input data rate.
4.5 Phase Acquisition Loop — The Phase Detector
The phase detector is a digital quadrature phase detector. It indicates whether the
input data is leading or lagging with respect to a clock that is in phase with the VCO
(I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop)
is locked, the input data transition is aligned to the falling edge of I-clk and the
output data is re-timed on the rising edge of I-clk. During high input jitter conditions
(>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra
phase correction signals will be generated which instructs the charge pump to
create larger frequency corrections for the VCO.
Figure 4-2: Phase Detector Characteristics
When the PA loop is active, the crystal frequency and the incoming data rate are
compared. If the resultant is more that 2%, the PLL is considered to be unlocked
and the system jumps to the FA loop.
i-PHASE ALIGNMENT
EDGE
DATA RE-TIMING
EDGE
q-PHASE ALIGNMENT
EDGE
0.25UI
0.8UI
I-clk
q-clk
INPUT DATA
WITH JITTER
RE-TIMED
OUTPUT DATA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

GS9076-CNE3

Mfr. #:
Buy GS9076-CNE3
Manufacturer:
Semtech
Description:
Video ICs QFN-64 pin
Lifecycle:
New from this manufacturer.
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