MP20075 – 3A, 1.05V-3.6V INPUT, DDR2/3/3L MEMORY TERMINATION REGUALTOR
MP20075 Rev. 1.2 www.MonolithicPower.com 4
7/15/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
PIN FUNCTIONS
Pin # Name Description
1 DDQ
Power input for VTT regulator. Bypass with a 10μF ceramic capacitor. It is normally
connected to the VDDQ of DDR2/3/3L/4 memory rail.
2 VTT
Power output for the VTT LDO. Output is a precision VREF/2 voltage that tracks VREF.
Recommended bypass is 2x10μF ceramic capacitors.
3
GND,
Exposed
Pad
The exposed pad and GND pin must be connected to the same ground plane.
4 VTTSEN Kelvin sensed feedback signal.
5 VDRV Chip bias Voltage. Connect to 3.3V supply and bypass with a 4.7μF capacitor.
6 REF LDO signal input for generating VDDQ/2 reference. Bypass with a 0.1μF capacitor.
7 EN
VTT regulator enable input. EN HIGH will enable the MP20075 requires 100k pull-up
resistor.
8 VTTREF
Precision buffered output for the system with a drive capability up to 10mA. The receiving
end of the DDR2/3/3L/4 memory cells requires this signal for their input comparator.
Bypass with a 0.1μF capacitor.
