7
LTC1278
RD (Pin 20): READ Input. This enables the output
drivers when CS is low.
CS (Pin 21): The CHIP SELECT input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is low when a conversion is in progress.
V
SS
(Pin 23): Negative Supply. –5V for bipolar opera-
tion. Bypass to AGND with 0.1µF ceramic. Analog
ground for unipolar operation.
AV
DD
(Pin 24): Positive Supply, 5V. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
A
IN
(Pin 1): Analog Input. 0V to 5V (Unipolar), ±2.5V
(Bipolar).
V
REF
(Pin 2): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 11 to 4): Three-State Data Outputs.
D11 is the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
DV
DD
(Pin 17 ): Digital Power Supply, 5V. Tie to AV
DD
pin.
SHDN (Pin 18): Power Shutdown.
CONVST (Pin 19): Conversion Start Signal. This active
low signal starts a conversion on its falling edge (to
recognize CONVST, CS has to be low).
PI FU CTIO S
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12-BIT CAPACITIVE DAC
COMPARATOR
2.42V REF
V
REF
C
SAMPLE
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
•
•
D11
D0
BUSY
CONTROL LOGIC
CSCONVST RDSHDN
INTERNAL
CLOCK
ZEROING
SWITCH
DV
DD
V
SS
AV
DD
(0V FOR UNIPOLAR MODE
OR –5V FOR BIPOLAR MODE)
A
IN
AGND
DGND
12
12
LTC1278 • BD
FU CTIO AL BLOCK DIAGRA
UU W
8
LTC1278
CONVERSION DETAILS
The LTC1278 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
input connects to the sample-and-hold
capacitor during the acquire phase, and the comparator
TEST CIRCUITS
Load Circuits for Output Float DelayLoad Circuits for Access Timing
3k C
L
DBN
DGND
A) HIGH-Z TO V
OH
(t
8
)
AND V
OL
TO V
OH
(t
6
)
C
L
DBN
3k
5V
B) HIGH-Z TO V
OL
(t
8
)
AND V
OH
TO V
OL
(t
6
)
DGND
LTC1278 TA08
3k 10pF
DBN
DGND
A) V
OH
TO HIGH-Z
10pF
DBN
3k
5V
B) V
OL
TO HIGH-Z
DGND
1278 • TA08
SHDN to CONVST Wake-Up Timing
t
3
SHDN
CONVST
LTC1278 • TC03
APPLICATIONS INFORMATION
WUU
U
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 200ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
V
DAC
LTC1278 F1
+
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
12-BIT
LATCH
COMPARATOR
SAMPLE
SI
A
IN
Figure 1. A
IN
Input
CS to RD Setup Timing
t
1
CS
RD
LTC1278 • TC01
CS to CONVST Setup Timing
t
2
CS
CONVST
LTC1278 • TC02
TI I G DIAGRA S
WU W
9
LTC1278
compare mode. The input switch switches C
SAMPLE
to
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the A
IN
input charge. The SAR contents (a 12-bit
data word) which represent the A
IN
are loaded into the
12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1278 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distor-
tion sine wave and analyzing the digital output using an
FFT algorithm, the ADC’s spectral content can be exam-
ined for frequencies outside the fundamental. Figure 2
shows a typical LTC1278 FFT plot.
a 500kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 250kHz.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 500kHz the LTC1278 maintains very good ENOBs up
to the Nyquist input frequency of 250kHz. Refer to Figure 3.
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20log
V
2
2
+ V
3
2
+ V
4
2
... + V
N
2
V
1
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through Nth harmonics. THD versus input
INPUT FREQUENCY (Hz)
10k
0
EFFECTIVE NUMBER OF BITS
S/(N+D) (dB)
3
5
7
10
100k 1M 2M
LT1278 G4
1
4
6
9
12
11
62
56
74
68
8
2
f
SAMPLE
= 500kHz
NYQUIST
FREQUENCY
Figure 3. Effective Bits and Signal-to-Noise + Distortion vs
Input Frequency
Figure 2. LTC1278 Nonaveraged, 4096 Point FFT Plot
APPLICATIONS INFORMATION
WUU
U
FREQUENCY (Hz)
0
120
AMPLITUDE (dB)
100
–80
–60
–40
–20
0
50k 100k 150k 200k
LTC1278 F2
250k
f
SAMPLE
= 500kHz ±5V
f
IN
= 97.045kHz

LTC1278-4CSW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit, 400ksps Sampling A/D Converter with Shutdown
Lifecycle:
New from this manufacturer.
Delivery:
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