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CY24242OXCT

P1-P3P4-P6P7-P9P10-P12P13-P15
CY24242
Document Number: 38-07268 Rev. *G Page 7 of 15
Absolute Maximum Ratings
[4]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not
implied. Maximum conditions for extended periods may affect reliability.
.
Parameter Description Rating Unit
V
DD
, V
IN
Voltage on any pin with respect to GND –0.5 to +7.0 V
T
STG
Storage Temperature –65 to +150 °C
T
A
Operating Temperature –55 to +125 °C
T
B
Ambient Temperature under Bias 0 to +70 °C
ESD
PROT
Input ESD Protection 2 (min.) kV
DC Electrical Characteristics
T
A
= 0°C to +70°C, V
DDQ3
= 3.3 V ± 10%
Parameter Description Test Condition Min Typ Max Unit
Supply Current
I
DDQ3
Supply Current (3.3 V) CPUCLK = 100 MHz Outputs
Loaded
[4]
––400mA
I
DDQ2
Supply Current (2.5 V) CPUCLK = 100 MHz Outputs
Loaded
[4]
––400mA
Logic Inputs
[5]
V
IL
Input Low Voltage – GND – 3 – 0.8 V
V
IH
Input High Voltage – 2.0 – V
DD
+.3 V
I
IL
Input Low Current
[6]
––––25µA
I
IH
Input High Current
[6]
–––10µA
Crystal Oscillator
V
TH
X1 Input Threshold Voltage
[7]
––1.5–V
C
LOAD
Load Capacitance, Imposed on
External Crystal
[8]
––14–pF
C
IN,X1
X1 Input Capacitance
[9]
Pin X2 unconnected – 28 – pF
Pin Capacitance/Inductance
C
IN
Input Pin Capacitance Except X1 and X2 – – 5 pF
C
OUT
Output Pin Capacitance – – – 6 pF
L
IN
Input Pin Inductance – – – 7 nH
Notes
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. CY24242 logic inputs have internal pull-up resistors.
6. X1 input threshold voltage (typical) is V
DDQ
/2.
7. All clock output loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
8. The CY24242 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
9. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
CY24242
Document Number: 38-07268 Rev. *G Page 8 of 15
AC Electrical Characteristics
T
A
= 0 °C to +70 °C, V
DD
= V
DDQ3
= 3.3 V ± 10%, f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock
output.
CPU Clock Outputs, CPU0:3
(Lump Capacitance Test Load = 20 pF, V
DDC
= 3.3 V)
Parameter Description Test Condition/Comments
CPU = 66 MHz CPU = 100 MHz
Unit
Min Typ Max Min Typ Max
t
P
Period Measured on rising edge at 1.5 V 15 – 15.5 10 – 10.5 ns
t
H
High Time Duration of clock cycle above 2.4 V 5.2 – – 3.0 – – ns
t
L
Low Time Duration of clock cycle below 0.4 V 5 – – 2.8 – – ns
t
R
Output Rise Edge Rate Measured from 0.4 V to 2.4 V 0.4 – 3.2 0.4 – 3.2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4 V to 0.4 V 0.4 – 3.2 0.4 – 3.2 V/ns
t
D
Duty Cycle Measured on rising and falling edge
at 1.5 V
45 – 55 45 – 55 %
t
JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5 V.
Maximum difference of cycle time
between two adjacent cycles.
– – 250 – – 250 ps
t
SK
Output Skew Measured on rising edge at 1.5 V – – 250 – – 250 ps
f
ST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage
reached within 1 ms from power-up.
Short cycles exist prior to frequency
stabilization.
– – 3 – – 3 ms
Z
o
AC Output Impedance Average value during switching
transition. Used for determining
series termination value.
– 20 – – 20 –
CY24242
Document Number: 38-07268 Rev. *G Page 9 of 15
SDRAM Clock Outputs, SDRAM0:3
(Lump Capacitance Test Load = 30 pF, V
DDC
= 3.3 V)
Parameter Description Test Condition/Comments
CPU = 66 MHz CPU = 100 MHz
Unit
Min Typ Max Min Typ Max
t
P
Period Measured on rising edge at 1.5 V 15 – 15.5 10 – 10.5 ns
t
H
High Time Duration of clock cycle above 2.4 V 5.2 – – 3.0 – – ns
t
L
Low Time Duration of clock cycle below 0.4 V 5 – – 2.8 – – ns
t
R
Output Rise Edge Rate Measured from 0.4 V to 2.4 V 0.4 – 3.2 0.4 – 3.2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4 V to 0.4 V 0.4 – 3.2 0.4 – 3.2 V/ns
t
D
Duty Cycle Measured on rising and falling edge
at 1.5 V
45 – 55 45 – 55 %
t
JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5 V.
Maximum difference of cycle time
between two adjacent cycles.
– – 250 – – 250 ps
t
SK
Output Skew Measured on rising edge at 1.5 V 100 300 100 350 ps
t
SK
CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs.
Measured on rising edge at 1.5 V.
– – 350 – – 350 ps
f
ST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage
reached within 1 ms from power-up.
Short cycles exist prior to frequency
stabilization.
– – 3 – – 3 ms
Z
o
AC Output Impedance Average value during switching
transition. Used for determining
series termination value.
– 20 – – 20 –
P1-P3P4-P6P7-P9P10-P12P13-P15

CY24242OXCT

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Manufacturer:
Cypress Semiconductor
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Phase Locked Loops - PLL Spectrum Clk Genratr COM
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