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MAX3881ECB+D

P1-P3P4-P6P7-P9P10-P11
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
4 _______________________________________________________________________________________
1
0.1
10 100 1000
JITTER TOLERANCE vs. INPUT VOLTAGE
0.3
0.2
MAX3881 toc04
INPUT VOLTAGE (mVp-p)
JITTER TOLERNCE (UIp-p)
0.5
0.4
0.7
0.8
0.6
0.9
0
SONET SPEC
JITTER FREQUENCY = 5MHz
JITTER FREQUENCY = 1MHz
10
-10
10
-8
10
-9
10
-6
10
-7
10
-4
10
-5
10
-3
8.0 8.5 9.0 9.5 10
BIT ERROR RATIO vs. INPUT VOLTAGE
MAX3881-05
INPUT VOLTAGE (mVp-p)
BIT ERROR RATIO
200
300
400
600
500
700
-50 0-25 25 50 75 100
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3881-06
TEMPERATURE (°C)
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
1.64ns/div
DATA
CLOCK
RECOVERED DATA AND CLOCK
MAX3881-01
2
23
- 1 PATTERN
140
150
160
170
180
190
200
-50 -25 0 25 50 75 100
SUPPLY CURRENT vs. TEMPERATURE
MAX3881-02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
V
CC
= +3.6V
V
CC
= +3.0V
10.0
0.1
1,000 10,000
1.0
JITTER FREQUENCY (kHz)
INPUT JITTER (UIp-p)
10010
JITTER TOLERANCE
MAX3881 toc03
C
F
= 0.1µF
C
F
= 1.0µF
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
_______________________________________________________________________________________ 5
NAME FUNCTION
1, 15, 16, 17,
25, 33, 41,
49, 57, 62,
64
GND Ground
PIN
Pin Description
2 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
3 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
4, 7, 10, 13,
20, 22, 24,
26, 28, 30,
32, 34, 36,
38, 40, 42,
44, 46, 48,
50, 52, 54,
56, 58, 60
V
CC
+3.3V Supply Voltage
5 PHADJ+
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
6 PHADJ-
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
8 SDI+ Positive Serial Data Input. 2.488Gbps data stream.
9 SDI- Negative Serial Data Input. 2.488Gbps data stream.
11 SLBI+ Positive System Loopback Input. 2.488Gbps data stream.
12 SLBI- Negative System Loopback Input. 2.488Gbps data stream.
14 SIS
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
18 PCLK+ Positive Parallel Clock PECL Output
19 PCLK- Negative Parallel Clock PECL Output
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PD0 to PD15
Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 2).
63
LOL
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pullup resistor).
The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881.
EP Exposed Pad
Ground. This must be soldered to a circuit board for proper electrical and thermal performance
(see Package Information).
MAX3881
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
6 _______________________________________________________________________________________
Detailed Description
The MAX3881 deserializer with clock recovery converts
2.488Gbps serial data to 16-bit-wide, 155Mbps parallel
data. The device combines a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
16-bit demultiplexer, clock divider, and PECL output
buffer (Figure 3). The PLL consists of a phase/frequen-
cy detector (PFD), a loop filter, and a voltage-controlled
oscillator (VCO). The MAX3881 is designed to deliver
the best combination of jitter performance and power
dissipation by using a differential signal architecture
and low-noise design techniques. The PLL recovers the
serial clock from the serial input data stream. The
demultiplexer generates a 16-bit-wide 155Mbps paral-
lel data output.
Input Amplifier
The input amplifiers on both the main data and system
loopback accept a differential input amplitude from
50mVp-p to 800mVp-p. The bit error ratio (BER) is bet-
ter than 1 x 10
-10
for input signals as small as 9.5mVp-p,
Figure 3. MAX3881 Functional Diagram
MAX3881
SDI+
AMP
PECL
LOL
50Ω
50Ω
MUX
PHASE &
FREQUENCY
DETECTOR
SDI-
SLBI+
AMP
SLBI-
SIS
V
CC
V
CC
LOOP
FILTER
VCO
16-BIT
DEMULTIPLEXER
D
Q
CK
PHADJ+ PHADJ- FIL+ FIL-
CLOCK
DIVIDER
PCLK+
PCLK-
PD15
PECL
PD1
PECL
PD0
PECL
TTL
0
I
0
I
P1-P3P4-P6P7-P9P10-P11

MAX3881ECB+D

Mfr. #:
Buy MAX3881ECB+D
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes Integrated Circuits (ICs)
Lifecycle:
New from this manufacturer.
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