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WM8781GEDS/RV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Production Data WM8781
w
PD, January 2012, Rev 4.5
7
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue Reference Levels
Midrail Reference Voltage VMID
AVDD to VMID and
VMID to VREFN
–4% AVDD/2 +4% V
Potential Divider Resistance R
VMID
50 kΩ
Buffered Reference Voltage VREFP
–4% AVDD/2 +4% V
VREF source current I
VREF
5 mA
VREF sink current I
VREF
5 mA
Supply Current
Analogue supply current
AVDD = 5V 32 mA
Digital supply current
DVDD = 3.3V 5 mA
Power Down
0.5 mA
Notes:
1. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter. Failure to
use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the
Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect
dynamic specification values.
2. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce
performance.
3. This high leakage current is due to the topology of the instate pads. The pad input is connected to the midpoint of an
internal resistor string to pull input to vmid if undriven.
TERMINOLOGY
1. Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the
digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these
results).
2. Dynamic range (dB) – DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
WM8781 Production Data
w
PD, January 2012, Rev 4.5
8
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C.
PARAMETER SYMBOL MIN TYP MAX UNIT
System Clock Timing Information
MCLK System clock pulse width high
T
MCLKL
11 ns
MCLK System clock pulse width low
T
MCLKH
11 ns
MCLK System clock cycle time
T
MCLKY
28 ns
MCLK duty cycle
T
MCLKDS
40:60 60:40
Table 1 Master Clock Timing Requirements
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Master Mode, fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
t
DL
0 10 ns
DOUT propagation delay from BCLK falling edge
t
DDA
0 10 ns
Table 2 Digital Audio Data Timing - Master Mode
Production Data WM8781
w
PD, January 2012, Rev 4.5
9
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
50 ns
BCLK pulse width high
t
BCH
20 ns
BCLK pulse width low
t
BCL
20 ns
LRCLK set-up time to BCLK rising edge
t
LRSU
10 ns
LRCLK hold time from BCLK rising edge
t
LRH
10 ns
DOUT propagation delay from BCLK falling edge
t
DD
0 10 ns
Table 3 Digital Audio Data Timing - Slave Mode
Note:
LRCLK should be synchronous with MCLK, although the WM8781 interface is tolerant of phase variations or jitter on these
signals.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

WM8781GEDS/RV

Mfr. #:
Buy WM8781GEDS/RV
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs STEREO ADC W/384FS MASTER MODE
Lifecycle:
New from this manufacturer.
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