MAX1115EKA+T

Input Voltage Range
Internal protection diodes that clamp the analog input
to V
DD
and GND allow the input pin (CH0) to swing
from (GND - 0.3V) to (V
DD
+ 0.3V) without damage.
However, for accurate conversions, the inputs must not
exceed (V
DD
+ 50mV) or be less than (GND - 50mV).
Input Bandwidth
The ADCs input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADCs sampling rate by
using undersampling techniques. Anti-alias filtering is
recommended to avoid high-frequency signals being
aliased into the frequency band of interest.
Serial Interface
The MAX1115/MAX1116 have a 3-wire serial interface.
The CNVST and SCLK inputs are used to control the
device, while the three-state DOUT pin is used to
access the conversion results.
The serial interface provides connection to microcon-
trollers (µCs) with SPI, QSPI, and MICROWIRE serial
interfaces at clock rates up to 5MHz. The interface sup-
ports either an idle high or low SCLK format. For SPI
and QSPI, set CPOL = CPHA = 0 or CPOL = CPHA = 1
in the SPI control registers of the µC. Figure 5 shows
the MAX1115/MAX1116 common serial-interface con-
nections. See Figures 6a6d for details on the serial-
interface timing and protocol.
MAX1115/MAX1116
Single-Supply, Low-Power, Serial 8-Bit ADCs
_______________________________________________________________________________________ 7
V
DD
I/O
SCK (SK)
MISO (SI)
GND
DOUT
SCLK
CONVST
GND
V
DD
0.1µF
1µF
CH0
ANALOG
INPUTS
MAX1115
MAX1116
CPU
V
DD
Figure 3. Typical Operating Circuit
GND
C
HOLD
CAPACITIVE DAC
V
DD
2
COMPARATOR
16pF
R
IN
6.5k
AUTO-ZERO
RAIL
TRACK
HOLD
CH0
Figure 4. Equivalent Input Circuit
CONVST
SCLK
DOUT
I/O
SCK
MISO
SS
a) SPI
CONVST
CONVST
SCLK
DOUT
CS
SCK
MISO
+3V
SS
b) QSPI
MAX1115
MAX1116
MAX1115
MAX1116
MAX1115
MAX1116
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
+3V
Figure 5. Common Serial-Interface Connections
MAX1115/MAX1116
Digital Inputs and Outputs
The MAX1115/MAX1116 perform conversions by using
an internal clock. This frees the µP from the burden of
running the SAR conversion clock, and allows the con-
version results to be read back at the µPs convenience
at any clock rate up to 5MHz.
The acquisition interval begins with the falling edge of
CNVST. CNVST can idle between conversions in either
a high or low state. If idled in a low state, CNVST must
be brought high for at least 50ns, then brought low to
initiate a conversion. To select V
DD
/2 for conversion,
the CNVST pin must be brought high and low for a
second time (Figures 6c and 6d).
Single-Supply, Low-Power, Serial 8-Bit ADCs
8 _______________________________________________________________________________________
ACTIVE POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE LOW IDLE LOW
CH0
t
CSH
t
CONV
t
cp
t
ccs
t
chz
t
cl
t
cd
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
t
csd
t
ch
Figure 6a. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle Low
ACTIVE POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE HIGH
IDLE HIGH
CH0
t
CSH
t
CONV
t
cp
t
ccs
t
chz
t
cl
t
cd
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
t
csd
t
ch
Figure 6b. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle High
After CNVST is brought low, allow 7.5µs for the conver-
sion to be completed. While the internal conversion is in
progress, DOUT is low. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 7). Data is
clocked out at SCLKs falling edge in MSB-first format
at rates up to 5MHz. Once all data bits are clocked out,
DOUT goes high impedance (100ns to 500ns after the
rising edge) of the eighth SCLK pulse.
SCLK is ignored during the conversion process. Only
after a conversion is complete will SCLK cause serial
data to be output. Falling edges on CNVST during an
MAX1115/MAX1116
Single-Supply, Low-Power, Serial 8-Bit ADCs
_______________________________________________________________________________________ 9
ACTIVE POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE LOW IDLE LOW
CH0
t
CSH
t
CONV
t
cp
t
ccs
t
CSL
t
chz
t
cl
t
cd
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
t
csd
t
ch
V
DD
2
V
DD
2
Figure 6c. Conversion and Interface Timing, Conversion on V
DD
/ 2 with SCLK Idle Low
ACTIVE POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE HIGHIDLE HIGH
CH0
t
CSH
t
CONV
t
cp
t
ccs
t
csl
t
chz
t
cl
t
cd
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
t
csd
t
ch
V
DD
2
V
DD
2
Figure 6d. Conversion and Interface Timing, Conversion on V
DD
/ 2 with SCLK Idle High

MAX1115EKA+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Single-Supply Low Power Serial 8-Bit
Lifecycle:
New from this manufacturer.
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