AS1345 – 20 18V, High Efficiency, DC-DC Step-Up Converter
PCB Layout
Carefully printed circuit layout is important for minimizing
ground bounce and noise. Keep the GND pin and ground pads
for the input and output capacitors as close together as
possible. Keep the connection to LX as short as possible. Locate
the feedback resistors as close as possible to the FB pin and
keep the feedback traces routed away from noisy areas such as
LX.
EMI and overall performance quality are affected by the PCB
layout. The high speed operation of the AS1345 demands
careful attention to board layout. Stated performance will be
difficult to achieve with careless layout. Figure 24 identifies the
high current paths during an operation cycle involving the
switching of the N-channel and P-channel internal switches.
The current paths between SWIN, VIN, C1, C2, C4, L1, D1 and
GND should be short and wide for lowest intrinsic resistive loss
and lowest stray inductance.
A large ground pin copper area will help to lower the chip
temperature. A multilayer board with a separate ground plane
is ideal, but not absolutely necessary.
Figure AS1345 – 24:
AS1345 - Inductor Current Paths
AS1345
D1
R2
PDRV
NDRV
FB
ILIM
L1
C2 C1
C3
0V
R3
RLOAD
SWIN
VDD
SWOUT LX
FB
GND
VBAT
VOUT
0V
Inductor Current Path NMOS-OFF, D1-ON
Load Current Path NMOS-OFF, D1-OFF
Inductor Current Path NMOS-ON, D1-OFF
