Datasheet
10/13
BD45xxx series BD46xxx series
TSZ02201-0R7R0G300010-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
18.Dec.2012 Rev.005
www.rohm.com
TSZ22111・15・001
●Application Information
Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the V
DD
pins reaches the applicable threshold voltage, the V
OUT
terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD45xxx series uses an open drain output
type, it is necessary to connect either a pull-up resistor to V
DD
or another power supply if needed [The output “High” voltage
(V
OUT
) in this case becomes V
DD
or the voltage of the other power supply].
Fig.15 (BD45xxx Type Internal Block Diagram) Fig.16 (BD46xxx Type Internal Block Diagram)
Reference Data
Examples of Leading (t
PLH
) and Falling (t
PHL
) Output
Part Number t
PLH
[ms] t
PHL
[µs]
BD45275G 50 18
BD46275G 50 18
VDD=2.2VÆ3.2V VDD=3.2VÆ2.2V
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
Timing Waveform
Example: The following shows the relationship between the input voltages V
DD
, the output voltage V
OUT
and ER terminal when
the input power supply voltage V
DD
is made to sweep up and sweep down (the circuits are those in Fig. 12 and 13).
1
When the power supply is turned on, the output is unstable from
after over the operating limit voltage (V
OPL
) until t
PHL
. Therefore it is
possible that the reset signal is not outputted when the rise time of
V
DD
is faster than t
PHL
.
2
When V
DD
is greater than V
OPL
but less than the reset release
voltage (V
DET
+ ∆V
DET
), the output voltages will switch to Low.
3
If V
DD
exceeds the reset release voltage (V
DET
+ ∆V
DET
), the
counter timer start and V
OUT
switches from L to H.
4
When more than the high level voltage is supplied to the ER
terminal, V
OUT
comes to “L” after t
PLH
delay time. Therefore, a time
when ER terminal is “H” is necessary for 100µsec or more.
5
When the ER terminal switches to Low, the counter timer starts
to operate, a delay of t
PLH
occurs, and V
OUT
switches from “L” to “H”.
6
If V
DD
drops below the detection voltage (V
DET
) when the power
supply is powered down or when there is a power supply fluctuation,
V
OUT
switches to L (with a delay of t
PHL
).
7
The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (∆V
DET
). The
system is designed such that the output does not toggle with power
supply fluctuations within this hysteresis width, preventing
malfunctions due to noise.
These time changes by the application and use it, please verify and confirm using practical applications.
Vref
R1
R2
R3
V
DD
GND
Oscillation
Circuit Counter
Timer
Q1
V
OUT
V
DD
Reset
ER
Q2
Q1
Vref
R1
R2
R3
V
DD
GND
Oscillation
Circuit Counter
Timer
V
OUT
Reset
ER
Fig.17 Timing Waveform
VDD
V
DET+ΔVDET
VDET
V
OPL
0V
tPHL
① ②
VOUT
tPLH
tPHL
tPLH
③ ④
VOL
VOH
VDD
tPLH
tPHL
⑥ ⑤
VEH
ER
⑦
