74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 13 May 2008 3 of 18
NXP Semiconductors
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
Fig 3. Logic diagram
001aae056
D
R
D
Q
FF8
Q7
D7
D
R
D
Q
FF7
Q6
D6
D
R
D
Q
FF6
Q5
D5
D
R
D
Q
FF5
Q4
D4
D
R
D
Q
FF4
Q3
D3
D
R
D
Q
FF3
Q2
D2
D
R
D
Q
FF2
Q1
D1
D
CPCPCPCP
CPCPCPCP
R
D
Q
FF1
Q0
D0
CP
MR
Fig 4. Functional diagram
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D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
FF1
TO
FF8
MR
CP
74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 13 May 2008 4 of 18
NXP Semiconductors
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20
74AHC273
74AHCT273
MR V
CC
Q0 Q7
D0 D7
D1 D6
Q1 Q6
Q2 Q5
D2 D5
D3 D4
Q3 Q4
GND CP
001aai066
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
001aai067
74AHC273
74AHCT273
Transparent top view
Q4
D3
Q3
D4
D2 D5
Q2 Q5
Q1 Q6
D1 D6
D0 D7
Q0 Q7
GND
CP
MR
V
CC
9
12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
GND
(1)
Table 2. Pin description
Symbol Pin Description
MR 1 master reset input (active LOW)
Q0 2 flip-flop output
D0 3 data input
D1 4 data input
Q1 5 flip-flop output
Q2 6 flip-flop output
D2 7 data input
D3 8 data input
Q3 9 flip-flop output
GND 10 ground (0 V)
CP 11 clock input (LOW-to-HIGH edge-triggered)
Q4 12 flip-flop output
D4 13 data input
D5 14 data input
Q5 15 flip-flop output
Q6 16 flip-flop output
74AHC_AHCT273_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 13 May 2008 5 of 18
NXP Semiconductors
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
= LOW-to-HIGH;
X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60 °C the value of P
tot
derates linearly at 4.5 mW/K.
D6 17 data input
D7 18 data input
Q7 19 flip-flop output
V
CC
20 supply voltage
Table 2. Pin description
…continued
Symbol Pin Description
Table 3. Function table
[1]
Operating mode Control Input Output
MR CP Dn Qn
Reset (clear) L X X L
Load ‘1’ H hH
Load ‘0’ H lL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
V
I
input voltage 0.5 +7.0 V
I
IK
input clamping current V
I
< 0.5 V
[1]
20 - mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+ 0.5 V
[1]
20 +20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+ 0.5 V) 25 +25 mA
I
CC
supply current - +75 mA
I
GND
ground current 75 - mA
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation T
amb
= 40 °C to +125 °C
[2]
- 500 mW

74AHCT273BQ,115

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops OCTAL D FLIP-FLOP
Lifecycle:
New from this manufacturer.
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