7 of 7 September 15, 2009
IDT 89HPES32NT8AG2 Product Brief
August 16, 2004August 16, 200
NOT AN OFFER FOR SALE
The information presented herein is subject to a Non-Disclosure Agreement and is for planning purposes only. Nothing contained in this presenta-
tion, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
®
Multicast
Multicast provides the ability to distribute data from one sender to multiple recipients simultaneously, off-loading processor cycles. The
PES32NT8AG2 supports up to 64 multicast groups and is fully compliant to the PCI-SIG Multicast ECN. This device also supports multicast across
switch partitions. Applications include storage mirroring and data or table update in communications control planes.
DMA
The DMA engines are used to transfer large amounts of data to and from system memory, off-loading the CPU cycles to focus on data processing
and manipulation, thereby increasing system performance. Along with NTB, the DMA engines can be used in Storage systems, large data or control
planes in networking equipment, High-Performance Computing platforms, and other embedded systems.
Isolated Port Clocking With SSC
In addition to the global clock network, the PES32NT8AG2 supports independent per-port clocking with SSC. Each port can operate in the
common or separate clock configuration. This IDT-unique capability provides greater flexibility in board design and configuration for modular systems
and connectivity across backplanes or cables. The SSC option allows EMI reduction to meet FCC standards, where applicable.
Hardware Error Containment
Traditional error handling mechanisms in most systems are handled by software in the root processor. Often, delays in error notification and
processing allow errors to spread through the system. A hardware error containment feature blocks the spreading of errors by isolating bad packets
and preventing them from leaving the switch, thereby avoiding system contamination. Benefits of hardware error containment include increased
robustness in high-availability systems and insurance against a variety of error-handling scenarios in arbritrary CPUs/endpoints.
Figure 11 Example of Hardware Error Containment Mechanism
Evaluation Kit and Software Tools
Evaluation kit 89KTPES32NT8AG2 will be available with evaluation board, user manual, schematic, and board layout.
The software package will include:
◆
PCIe Browser: GUI application to read/write to PCIe switch registers
◆
Switch Partitioning API: Allows dynamic reconfiguration of switch partitioning in Gen2 system interconnect switches
◆
Multicast API: Allows multicast configuration in Gen2 system interconnect switches
◆
DMA Driver: Activates the interface to DMA engines in PCIe switch
◆
System Interconnect software: Connects multiple processors using PCIe as the system interconnect
◆
Hot Swap Device Driver: Supports the hot insertion/removal of PCIe devices including switches
CPU
Switch
I/O or Line
Cards
!
!
CPU
Switch
I/O or Line
Cards
!!
!!
