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89H32NT8AG2ZCHLI8

P1-P3P4-P6P7-P7
4 of 7 September 15, 2009
IDT 89HPES32NT8AG2 Product Brief
Applications
PES32NT8AG2 is optimized for storage, communications control
plane, embedded systems and high-port PCI Express fanout applica-
tions. Applications shown here are generic to IDT’s Gen2 PCIe switch
family.
Storage Applications
Figure 2 Storage Redundancy Model
Large RAID storage systems, either direct-attached or SAN/NAS
attached, are generally built with redundancy. PCI Express switches are
used to connect CPUs to I/O controllers and across the redundancy
trunks, as illustrated in Figure 2. I/O controllers can be SAS, SATA, Fibre
Channel, or some combination of these. NTB functions enable commu-
nications across PCI Express domains and allow data exchanges and
synchronization across trunks. Additional NTB ports can also be
connected to intelligent I/O cards hosting embedded processors.
Communications Control Plane Applications
High port count, dynamic switch partitioning configuration, and
multiple NTB ports enable many possible communications control
configurations. Some common configurations are depicted below.
High Fanout
A straightforward use of the switch is to fan out to many different line
cards as illustrated in Figure 3. Cascading with another Gen 2 PCIe
switch will allow more than twenty-three x1 downstream ports.
Figure 3 High Fanout Usage Model
I/O
CPU
NTB P2P
P2PP2PP2P
NTB
I/OI/O
Intelligent
I/O
PES32NT8G2
x4 x4 x4 x4
x8
I/O
CPU
NTBP2P
P2P P2P P2P
NTB
I/O I/O
Intelligent
I/O
PES32NT8G2
x4 x4 x4 x4
x8 x8
NTBNTB
I/O
CPU
NTB P2P
P2PP2PP2P
NTB
I/OI/O
Intelligent
I/O
PES32NT8G2
x4 x4 x4 x4
x8
I/O
CPU
NTBP2P
P2P P2P P2P
NTB
I/O I/O
Intelligent
I/O
PES32NT8G2
x4 x4 x4 x4
x8 x8
NTBNTB
x4
CPU
42 x1
PES32NT24G2
PES32NT24G2
x4
To FPGA or ASIC
x4
CPUCPU
42 x1
PES32NT24G2
PES32NT24G2
x4
To FPGA or ASIC
Advanced Failover System
Dual host control with failover (shown in Figure 4) ensures reliability
and availability of systems in case of CPU failure. NTB across domains
allows active-active dual host topology, where both CPUs can access all
the downstream line cards. If the primary CPU fails, dynamic switch
partitioning capability can allow reallocation of downstream ports to the
secondary CPU and maintain continuity of operation.
Figure 4 Dual-Host Failover System
Dual-Star Topology
A dual-star topology, shown in Figure 5, ensures that no single node
or connection failure will bring down the system. Each I/O or line card
has connectivity to one primary CPU and also backup connectivity to a
secondary controller via an NTB port. If failure occurs, the NTB port can
be reallocated via dynamic reconfiguration of the line card switch while
the secondary CPU takes over. A high number of ports will allow the
switch to connect to many line cards.
Figure 5 Dual-Star Topology
Active/
Primary
CPU or Card
Active/
Secondary
CPU or Card
Upstream
x4
NTB
x4
20 x1
PES32NT24G2
NTBNTB
P2P
P2PP2PP2P
…
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
Line Card
Local
Devic es
FPGA /
NPU /
ASIC
Line Card
Local
Devices
…
Before Failover
After Failover
Active/
Primary
CPU or Card
Active/
Secondary
CPU or Card
Upstream
x4
NTB
x4
20 x1
PES32NT24G2
NTB
NTB
P2P
P2PP2PP2P
…
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
Line Card
Local
Devi ces
FPGA /
NPU /
ASIC
Line Card
Local
Devices
…
Active/
Primary
CPU or Card
Active/
Secondary
CPU or Card
Upstream
x4
NTB
x4
20 x1
PES32NT24G2
NTBNTB
P2P
P2PP2PP2P
…
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
Line Card
Local
Devic es
FPGA /
NPU /
ASIC
Line Card
Local
Devices
…
Active/
Primary
CPU or Card
Active/
Secondary
CPU or Card
Upstream
x4
NTB
x4
20 x1
PES32NT24G2
NTBNTB
P2PP2P
P2PP2PP2P
…
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
Line Card
Local
Devic es
FPGA /
NPU /
ASIC
FPGA /
NPU /
ASIC
Line Card
Local
Devic es
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
FPGA /
NPU /
ASIC
Line Card
Local
Devices
…
Before Failover
After Failover
Active/
Primary
CPU or Card
Active/
Secondary
CPU or Card
Upstream
x4
NTB
x4
20 x1
PES32NT24G2
NTB
NTB
P2P
P2PP2PP2P
…
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
Line Card
Local
Devi ces
FPGA /
NPU /
ASIC
Line Card
Local
Devices
…
Active/
Primary
CPU or Card
Active/
Secondary
CPU or Card
Upstream
x4
NTB
x4
20 x1
PES32NT24G2
NTB
NTB
P2P
P2PP2PP2P
…
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
Line Card
Local
Devi ces
FPGA /
NPU /
ASIC
FPGA /
NPU /
ASIC
Line Card
Local
Devi ces
FPGA /
NPU /
ASIC
Line Card
Local
Devices
FPGA /
NPU /
ASIC
FPGA /
NPU /
ASIC
Line Card
Local
Devices
…
Before Failover After Failover
Active/
Primary
CPU or Card
Standby/
Secondary
CPU or Card
x4 x4
22 x1
NTB
3-port NT
sw it ch
IO /
FPGA /
NPU
NTB
P2P
NTB
P2P
P2PP2 PP2P
…
P2PP2PP2P
…
…
NTB
3-port NT
switch
IO /
FPGA /
NPU
NTB
3-po rt NT
switch
IO /
FPGA /
NPU
PES32NT24G2
Active/
Primary
CPU or Card
Standby/
Secondary
CPU or Card
x4 x4
22 x1
NTB
3-p o rt NT
switch
IO /
FPGA /
NPU
NTB
P2P
NTB
P2 P
P2PP2PP2P
…
P2PP2PP2P
…
…
NTB
3-port NT
switch
IO /
FPGA /
NPU
NTB
3-port NT
switch
IO /
FPGA /
NPU
PES32NT24G2
NTB
Reallocated
Before Failover After Failover
Active/
Primary
CPU or Card
Standby/
Secondary
CPU or Card
x4 x4
22 x1
NTB
3-port NT
sw it ch
IO /
FPGA /
NPU
NTB
P2P
NTB
P2P
P2PP2 PP2P
…
P2PP2PP2P
…
…
NTB
3-port NT
switch
IO /
FPGA /
NPU
NTB
3-po rt NT
switch
IO /
FPGA /
NPU
PES32NT24G2
Active/
Primary
CPU or Card
Standby/
Secondary
CPU or Card
x4 x4
22 x1
NTB
3-port NT
sw it ch
IO /
FPGA /
NPU
NTB
P2P
NTB
P2P
P2PP2 PP2P
…
P2PP2PP2P
…
…
NTB
3-port NT
switch
IO /
FPGA /
NPU
NTB
3-po rt NT
switch
IO /
FPGA /
NPU
PES32NT24G2
Active/
Primary
CPU or Card
Standby/
Secondary
CPU or Card
x4 x4
22 x1
NTB
3-p o rt NT
switch
IO /
FPGA /
NPU
NTB
P2P
NTB
P2 P
P2PP2PP2P
…
P2PP2PP2P
…
…
NTB
3-port NT
switch
IO /
FPGA /
NPU
NTB
3-port NT
switch
IO /
FPGA /
NPU
PES32NT24G2
NTB
Reallocated
Active/
Primary
CPU or Card
Standby/
Secondary
CPU or Card
x4 x4
22 x1
NTB
3-p o rt NT
switch
IO /
FPGA /
NPU
NTB
P2P
NTB
P2 P
P2PP2PP2P
…
P2PP2PP2P
…
…
NTB
3-port NT
switch
IO /
FPGA /
NPU
NTB
3-port NT
switch
IO /
FPGA /
NPU
PES32NT24G2
NTB
Reallocated
5 of 7 September 15, 2009
IDT 89HPES32NT8AG2 Product Brief
Feature Descriptions & Benefits
Switch Partitioning
Switch partitioning is an innovative and unique IDT feature that
allows a switch to be statically or dynamically reconfigured into multiple
independent logical switches within a single physical device.
PES32NT8AG2 can support up to 8 partitions. Any port can be an
upstream port or downstream port and any root can have zero, one, or
more downstream ports associated with its partition (see Figure 6). The
partition configuration can be done statically or dynamically by writing
into the switch configuration registers via configuration EEPROM, I
2
C
interface, or one of the roots.
Figure 6 Example of Switch Partitioning Logical View
Switch partitioning enables a number of applications, allowing unique
benefits and differentiating value proposition for your products. See
Table 1 for a partial list of these benefits.
Replacing Multiple Discrete Switches
When switch partitioning is configured with multiple independent PCI
Express domains, it can replace multiple discrete PCI Express switches,
providing savings in cost, power, and board space.
Application Benefits
Replacing multiple discrete
switches
Saves power, space and cost over
multiple discrete PCIe switches
Bandwidth balancing in multi-root
multi processor systems
Improved performance through
optimal allocation of system
resources
Flexible slot mapping Saves power, space and cost over
PCIe signal switch solutions
Enables configurations that are
not practical using PCIe signal
switches
Port failover in high availability
systems
Provides greater flexibility than
movable upstream port or
upstream port failover
Table 1 Switch Partitioning Applications and Benefits
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
P2P P2P P2P
P2P
P2P P2P P2P
P2P
P2P P2P P2P
P2P
P2P P2P P2P
P2P
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
P2P P2P P2P
P2P
P2P P2P P2P
P2P
P2P P2 P P2P
P2P
P2P P2 P P2P
P2P
P2P P2P P2P
P2P
P2P P2P P2P
P2P
P2P P2P P2P
P2P
P2P P2P P2P
P2P
Bandwidth Balancing
Dynamic switch partitioning can be utilized to perform I/O bandwidth
balancing to optimize overall system throughput (Figure 7). A multi-root
system, such as in bladed systems, may have unbalanced traffic density
across its I/O cards. System bandwidth balancing can be performed by
dynamically re-allocating low-traffic or idle I/Os to heavy traffic density
partitions from the software application layer.
Figure 7 Dynamic Redistribution of I/Os to Optimize System Bandwidth
Flexible Slot Mapping for Hardware Re-Use
The flexibility of port mapping in switch partitioning allows maximum
hardware re-use for multiple variants of product line configurations to
meet the customized needs of your end customers, saving cost and
improving time to market.
Figure 8 below illustrates a 2-socket CPU vs. a 4-socket CPU config-
uration using the same hardware platform with a different switch parti-
tioning setup.
Figure 8 Example of Flexible Slot Mapping
Advanced Failover
Multi-root systems with high availability requirement can take advan-
tage of dynamic switch partitioning by re-allocating downstream ports to
a standby/secondary root upon failure (Figure 9). The device provides a
built-in automatic failover mechanism by specifying failover configuration
registers. Failover can be initiated by software, external signal pins, or
by a watchdog timer.
89HPES32NT24G2
64-lane, 16-port PCIe Gen2
Sys tem Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/ O I/O I/O I/O
Initial System State
89HPES32NT24G2
64-lane, 16-port PC Ie Gen2
System Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/ O I/O I/O
Re-allocated Resources
89HPES32NT24G2
64-lane, 16-port PCIe Gen2
Sys tem Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/ O I/O I/O I/O
89HPES32NT24G2
64-lane, 16-port PCIe Gen2
Sys tem Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/ O I/O I/O I/O
Initial System State
89HPES32NT24G2
64-lane, 16-port PC Ie Gen2
System Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/ O I/O I/O
Re-allocated Resources
“Northbridge” /
I/O Controller
89HPES32NT24G2
64-lane, 16-port PCIe Gen2
System Inter connec t Switch
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
CPU CPU
“Northbridge” /
I/O Controller
CPU CPU
“Northbridge” /
I/O Controller
89HPES32NT24G2
64-lane, 16-port PCIe Gen2
System Inter connec t Switch
I/O I/O I/O I/O I/ O I/O I/O I/ O I/O I/O I/O I/O
CPU CPU
4 Socket Server—Base Design 2 Socket Server—Reduced Cost Design
“Northbridge” /
I/O Controller
89HPES32NT24G2
64-lane, 16-port PCIe Gen2
System Inter connec t Switch
I/O I/ O I/O I/O I/O I/O I/O I/O I/O I/O I/ O I/O
CPU CPU
“Northbridge” /
I/O Controller
CPU CPU
“Northbridge” /
I/O Controller
89HPES32NT24G2
64-lane, 16-port PCIe Gen2
System Inter connec t Switch
I/O I/O I/O I/O I/ O I/O I/O I/ O I/O I/O I/O I/O
CPU CPU
4 Socket Server—Base Design 2 Socket Server—Reduced Cost Design
6 of 7 September 15, 2009
IDT 89HPES32NT8AG2 Product Brief
Figure 9 Example of Advanced Port Failover
Non-Transparent Bridging (NTB)
A non-transparent bridge (NTB) is required when two PCI Express domains need to communicate with each other. The main function of the NTB
block is to initialize and translate addresses and device IDs to allow data exchange across PCI Express domains. The major functionalities of the NTB
block are summarized in Table 2 .
Each switch partition can have its own NTB port and can communicate with other partitions as well as NTB ports that connect to an external
domain.
Figure 10 Possible Configuration of NTB Ports
Function Number Description
NTB ports Up to 8 Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots.
Mapping table
entries
Up to 64 for entire
device
Each device can have up to 64 masters ID for address and ID translations
Mapping windows Six 32-bits or three
64-bits
Each NT port has six BARs, where each BAR opening an NT window to another domain
Address translation Direct-address and
lookup table trans-
lations
Lookup-table translation maps the BAR address to an entry in a lookup-table memory up to 64, pro-
viding more flexibility in address translation
Doorbell registers 32 bits Doorbell register is used for event signaling between domains, where an outbound doorbell bit sets a
corresponding bit at the inbound doorbell in the other domain
Message registers 4 inbound and out-
bound registers of
32-bits
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain
Table 2 Non-Transparent Bridge Function Summary
89HPES32NT24G2
64-lane, 1 6-port P CIe G en2
System Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Initial System State
89HPES32NT24G2
64-lan e, 16 -port P CIe Gen2
System Interconnec t Switc h
ROOT ROOTROOTROOT
I/O I/ O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Fail-over System State
X
89HPES32NT24G2
64-lane, 1 6-port P CIe G en2
System Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
89HPES32NT24G2
64-lane, 1 6-port P CIe G en2
System Interconnect Switch
ROOT ROOTROOTROOT
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Initial System State
89HPES32NT24G2
64-lan e, 16 -port P CIe Gen2
System Interconnec t Switc h
ROOT ROOTROOTROOT
I/O I/ O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Fail-over System State
X
PCI-PCI
Bridge
Virtual PCI Bus
PCI-PCI
Bridge
PCI-PCI
Bridge
PCI-PCI
Bridge
NTB
PCI-PCI
Bridge
PCI-PCI
Bridge
PCI-PCI
Bridge
NTB
PCI-PCI
Bridge
PCI-PCI
Bridge
NTB
Upstream Ports
NTB
NTB Ports
Across Partitions
Partition Without
NTB
PCIe Switch
PCI-PCI
Bridge
Virtual PCI Bus
PCI-PCI
Bridge
PCI-PCI
Bridge
PCI-PCI
Bridge
Virtual PCI Bus
PCI-PCI
Bridge
PCI-PCI
Bridge
PCI-PCI
Bridge
NTB
PCI-PCI
Bridge
PCI-PCI
Bridge
PCI-PCI
Bridge
NTB
PCI-PCI
Bridge
PCI-PCI
Bridge
NTB
Upstream Ports
NTB
NTB Ports
Across Partitions
Partition Without
NTB
PCIe SwitchPCIe Switch
P1-P3P4-P6P7-P7

89H32NT8AG2ZCHLI8

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PCI Interface IC PCIE SWITCH
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