MAX6954
4-Wire Interfaced, 2.7V to 5.5V LED Display
Driver with I/O Expander and Key Scan
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inputs: clock (CLK), chip select (CS), and data in (DIN),
and one output, data out (DOUT). CS must be low to
clock data into or out of the device, and DIN must be
stable when sampled on the rising edge of CLK. DOUT
is stable on the rising edge of CLK. Note that while the
SPI protocol expects DOUT to be high impedance
when the MAX6954 is not being accessed, DOUT on
the MAX6954 is never high impedance.
CLK and DIN may be used to transmit data to other
peripherals. The MAX6954 ignores all activity on CLK
and DIN except when CS is low.
Control and Operation Using the 4-Wire Interface
Controlling the MAX6954 requires sending a 16-bit
word. The first byte, D15 through D8, is the command,
and the second byte, D7 through D0, is the data byte
(Table 5).
Connecting Multiple MAX6954s to the 4-Wire Bus
Multiple MAX6954s may be daisy-chained by connect-
ing the DOUT of one device to the DIN of the next, and
driving CLK and CS lines in parallel (Figure 2). Data at
DIN propagates through the internal shift registers and
appears at DOUT 15.5 clock cycles later, clocked out
on the falling edge of CLK. When sending commands
to daisy-chained MAX6954s, all devices are accessed
at the same time. An access requires (16 x n) clock
cycles, where n is the number of MAX6954s connected
together. To update just one device in a daisy-chain,
the user can send the no-op command (0x00) to the
others. Figure 3 is the MAX6954 timing diagram.
The MAX6954 is written to using the following
sequence:
1) Take CLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take CS high (while CLK is still high after clocking in
the last data bit).
5) Take CLK low.
Figure 4 shows a write operation when 16 bits are
transmitted.
If fewer or greater than 16 bits are clocked into the
MAX6954 between taking CS low and taking CS high
again, the MAX6954 stores the last 16 bits received,
including the previous transmission(s). The general
case is when n bits (where n > 16) are transmitted to
the MAX6954. The last bits are comprising bits {n-15} to
{n}, are retained, and are parallel loaded into the 16-bit
latch as bits D15 to D0, respectively (Figure 5).
