4
ICS93716
0420H—09/10/08
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to V
DD
+ 0.5V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120, C
L
=15pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current I
IH
V
I
= V
DD
or GND 5 µA
Input Low Current I
IL
V
I
= V
DD
or GND 5 µA
I
DD2.5
R
L
= 120, C
L
= 0pf @ 170MHz
250 350 mA
I
DDPD
C
L
= 0pf 65 90 mA
Input Clamp Voltage V
IK
V
DDQ
= 2.3V Iin = -18mA -1.2
V
I
OH
= -1 mA V
DD
- 0.1 V
I
OH
= -12 mA 1.7 V
I
OL
=1 mA 0.1 V
I
OL
=12 mA 0.6 V
Input Capacitance
1
C
IN
V
I
= GND or V
DD
3pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DD
3pF
1
Guaranteed b
y
desi
g
n at 233MHz, not 100% tested in production.
Operating Supply
Current
High-level output
voltage
V
OH
Low-level output voltage V
OL
5
ICS93716
0420H—09/10/08
DC Electrical Characteristics
(
see note1
)
T
A
= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
DDQ
, A
VDD
2.3 2.5 2.7 V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.4 V
DD
/2 - 0.18 V
SCLK, SDATA -0.3 0.7 V
CLK_INT, CLK_INC, FB_INC,
FB_INT
V
DD
/2 + 0.18 2.1 V
SCLK, SDATA 1.7 5 V
DC input signal voltage
(note 2)
V
IN
-0.3 V
DD
+ 0.3 V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36 V
DD
+ 0.6 V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.7 V
DD
+ 0.6 V
Output differential cross-
voltage (note 4)
V
OX
V
DD
/2 - 0.15 V
DD
/2 + 0.15 V
Input differential cross-
voltage (note 4)
V
IX
V
DD
/2 - 0.2 V
DD
/2 V
DD
/2 + 0.2 V
High Impedance
Output Current
I
OZ
V
DD
=2.7V, V
OUT
=V
DD
or GND 0.1 ±5
µ
A
Operating free-air
temperature
T
A
085°C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage V
IL
High level input voltage V
IH
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC excursion of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal crosses.
6
ICS93716
0420H—09/10/08
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, were
the cycle (t
c
) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
Timing Requirements
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120
, C
L
=15pF (unless otherwise
PARAMETER SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency
3
freq
op
33 233 MHz
Application Frequency
Range
3
freq
App
60 170 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
100 µs
Switching Characteristics
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120 , C
L
=15pF (unless otherwise stated)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Low-to high level
propa
g
ation dela
y
time
t
PLH
1
CLK_IN to any output 5.5 ns
High-to low level propagation
dela
y
time
t
PHL
1
CLK_IN to any output 5.5 ns
Dut
y
C
y
cle DC 49 51 %
Input clock slew rate t
sl
(
I
)
14v/ns
C
cle to C
cle Jitter
1
t
c
y
c
-t
c
y
c
100MHz < f < 170MHz 50 65 ps
C
cle to C
cle Jitter
1
t
c
y
c
-t
c
y
c
f=66MHz 72 75 ps
Phase error
t
(p
hase error
)
4
-150 0 150 ps
Output to Output Skew t
skew
75 100 ps
Rise Time, Fall Time t
r
, t
f
See figure 8 550 950 ps

93716BFLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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