Data Sheet ADM101E
CIRCUIT DESCRIPTION
The internal circuitry consists of three main sections. These are:
1. A charge pump dc-to-dc converter.
2. 5 V logic to EIA-232 driver.
3. EIA-232 to 5 V logic receiver.
CHARGE PUMP DC-DC CONVERTER
The dc-dc converter generates a negative supply voltage from
the 5 V supply, thus removing the need for a separate −5 V rail.
It consists of an on-chip 200 kHz oscillator, switching matrix
and two external capacitors, as shown in Figure 9.
Figure 9. Charge Pump DC–DC Converter
When S1 and S2 are closed, S3 and S4 are open, and C1 charges
to +V
CC
. S1 and S2 are then opened, while S3 and S4 are closed
to connect C1 across C2, dumping charge into C2. Since the
positive terminal of C2 is at ground, a negative voltage will be
built up on its negative terminal with each cycle of the oscilla-
tor. This voltage depends on the current drawn from C2. If the
current is small, the voltage will be close to −V
CC
, but will fall as
the current drawn increases.
CHARGE PUMP CAPACITORS AND SUPPLY
DECOUPLING
For proper operation of the charge pump, the capacitors should
have an equivalent series resistance (ESR) less than 1 Ω. As the
charge pump draws current pulses from V
CC
, the V
CC
decoupling
capacitor should also have low ESR. The V
CC
decoupling capacitor
and V– reservoir capacitor should also have low ESR because
they determine how effectively ESD pulses are clamped to V
CC
or V− by the on-chip clamp diodes. Tantalum or monolithic
ceramic capacitors are suitable for these components. If using
tantalum capacitors, do not forget to observe polarity.
TRANSMITTER (DRIVER) SECTION
The driver converts 5 V logic input levels into RS-232 compatible
output levels. With V
CC
= 5 V and driving an EIA-232 load, the
output voltage swing is typically ±4.2 V.
RECEIVER SECTION
The receivers are inverting level-shifters that accept EIA-232
input levels and translate them into 5 V logic output levels. The
inputs have internal 5 kΩ pull-down resistors to ground and are
also protected against overvoltages of up to ±25 V. The guaranteed
switching thresholds are 0.8 V minimum and 2.8 V maximum.
An unconnected receiver input is pulled to 0 V by the internal
5 kΩ pull-down resistor. This, therefore, results in a Logic 1 output
level for unconnected inputs or for inputs connected to GND.
The receivers have Schmitt trigger input with a hysteresis level
of 0.25 V. This ensures error-free reception for both noisy
inputs and for inputs with slow transition times.
Rev. B | Page 9 of 12
