4
AT17LV65A/128A/256A/512A/002A
2322D–CNFG–07/02
Device Description The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external controller.
The configuration EEPROM’s RESET/OE
and nCS pins control the tri-state buffer on
the DATA output pin and enable the address counter and the oscillator. When
RESET/OE
is driven Low, the configuration EEPROM resets its address counter and tri-
states its DATA pin. The nCS pin also controls the output of the AT17A series configura-
tor. If nCS is held High after the RESET/OE
pulse, the counter is disabled and the DATA
output pin is tri-stated. When nCS is driven subsequently Low, the counter and the
DATA output pin are enabled. When RESET/OE
is driven Low again, the address
counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET
/OE.