ICS91730
LOW EMI, SPREAD MODULATING, CLOCK GENERATOR
IDT®
LOW EMI, SPREAD MODULATING, CLOCK GENERATOR 3
ICS91730 REV F 061611
Table 1: Frequency Configuration (see I2C Byte0)
Above is the hard coded 5 bit (32 entry) ROM table.
FS3:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS4 can also be decoded from FS_IN1
latched input hardware pins.
FS_IN1
→ FS4. Upon power-up the default is to use hardware selection of FS_IN1 latched value.
FS3 = 0, FS2 = 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1).
To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power up
default of FS_IN1 = 1 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software selection by
switching this bit to a ‘1’ and then program the desired percentage by changing byte0 bits 7:3.
Sprd Typ
Sprd %
00000 0.60
00001
0.80
00010
1.00
00011 1.25
00100 1.50
00101
2.00
00110 0.50
00111
1.00
01000 0.60
01001 1.00
01010
-0.80
01011CTR SPD
+/-0.3
01100
1.50
01101
1.75
01110 2.00
01111 2.50
10000 3.00
10001
1.25
10010 0.40
10011 0.50
10100 0.70
10101 1.00
10110 1.20
10111 1.50
11000 0.60
11001 0.80
11010 1.00
11011
1.25
11100
1.50
11101
2.00
11110 0.50
11111
1.00
DOWN
SPREAD
(-)
DOWN
SPREAD
(-)
48in/48out
66in/66out
DOWN
SPREAD
(-)
CENTER
SPD (+/-)
14in/27out
DOWN
SPREAD
(-)
CENTER
SPD (+/-)
14in/14out
27in/27out
CENTER
SPD (+/-)
