W78C32C/W78C032C
- 10 -
6.3.2 Program Fetch Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Address Valid to ALE Low TAAS
1 T
CP-∆
- - nS 4
Address Hold after ALE Low TAAH
1 T
CP-∆
- - nS 1, 4
ALE Low to
Low
T
APL
1 T
CP-∆
- - nS 4
Low to Data Valid
T
PDA - - 2 TCP nS 2
Data Hold after
High
T
PDH 0 - 1 TCP nS 3
Data Float after
High
T
PDZ 0 - 1 TCP nS
ALE Pulse Width TALW
2 T
CP-∆
2 T
CP - nS 4
Pulse Width
T
PSW
3 T
CP-∆
3 T
CP - nS 4
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP.
3. Data have been latched internally prior to
going high.
4. "∆" ( due to buffer driving delay and wire loading) is 20 nS.
6.3.3 Data Read Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
ALE Low to
Low
T
DAR
3 T
CP-∆
-
3 TCP+∆
nS 1, 2
Low to Data Valid
T
DDA - - 4 TCP nS 1
Data Hold after
High
T
DDH 0 - 2 TCP nS
Data Float after
High
T
DDZ 0 - 2 TCP nS
Pulse Width
T
DRD
6 T
CP-∆
6 T
CP - nS 2
Notes:
1. Data memory access time is 8 T
CP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
