CM3202-02DE Datasheet CM3212-02DE, CM3202-02DE | P7-P9

CM3202−02

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TYPICAL OPERATING CHARACTERISTICS (Cont’d)

DDQ

0.5A/div

DDQ

0.1V/div

0.5A/div

0.1V/div

TIME (0.2ms/div) TIME (0.2ms/div)

-0.75A

VDDQ Transient Response VTT Transient Response

= 3.3V

APPLICATION INFORMATION

Powering DDR Memory

Double−Data−Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic

systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle

versus one. DDR SDRAMs transmit data at both the rising and falling edges of the memory bus clock.

DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power−supply rejection, while

reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management

architecture than previous RAM technology.

Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface

signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by

lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use

of a termination voltage, V

. SSTL_2 is an industry standard defined in JEDEC document JESD8−9. SSTL_2 maintains

high−speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM

specification in JESD79C.

DDR memory requires three tightly regulated voltages: V

DDQ

, V

, and V

REF

(see Typical DDR terminations, Class II). In

a typical SSTL_2 receiver, the higher current V

DDQ

supply voltage is normally 2.5 V with a tolerance of ±200 mV. The active

bus termination voltage, V

, is half of V

DDQ

. V

REF

is a reference voltage that tracks half of V

DDQ

±1%, and is compared with

the V

terminated signal at the receiver. V

must be within ±40 mV of V

REF

Figure 1. Typical DDR Terminations, Class II

−

VDDQ VTT (=VDDQ/2) VDDQ

VREF (=VDDQ/2)

Receiver

Transmitter

LineRs = 25

Rt = 25

CM3202−02

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APPLICATION INFORMATION (Cont’d)

The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but

does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume

16.2 mA to achieve the 405 mV minimum over V

needed at the receiver:

terminaton

405mV

Rt(25W)

+ 16.2mA

A typical 64 Mbyte SSTL−2 memory system, with 128 terminated lines, has a worst−case maximum V

supply current up

to ±2.07 A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if

they ever occur at all. These high current peaks can be handled by the V

external capacitor. In a real memory system, the

continuous average V

current level in normal operation is less than ±200 mA.

The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers

and other circuitry. The current level typically stays within a range of 0.5 A to 1 A, with peaks up to 2 A or more, depending

on memory size and the computing operations being performed.

The tight tracking requirements and the need for V

to sink, as well as source, current provide unique challenges for

powering DDR SDRAM.

CM3202−02 Regulator

The CM3202−02 dual output linear regulator provides all of the power requirements of DDR memory by combining two

linear regulators into a single TDFN−8 package. VDDQ regulator can supply up to 2 A current, and the two−quadrant V

termination regulator has current sink and source capability to ±2 A. The VDDQ linear regulator uses a PMOS pass element

for a very low dropout voltage, typically 500 mV at a 2 A output. The output voltage of V

DDQ

can be set by an external voltage

divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any

change of the load, from high current to low current or inversely. The second output, V

, is regulated at V

DDQ

/2 by an internal

resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The V

regulator

can source, as well as sink, up to 2 A current. The CM3202−02 is designed for optimal operation from a nominal 3.3 VDC bus,

but can work with VIN up to 5 V. When operating at higher VIN voltages, attention must be given to the increased package

power dissipation and proportionally increased heat generation. Limited by the package thermal resistance, the maximum

output current of the device at higher VIN cannot exceed the limit imposed by the maximum power dissipation value.

REF

is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate V

REF

can be created with a simple voltage divider of precision, matched resistors from V

DDQ

to ground. A small ceramic bypass

capacitor can also be added for improved noise performance.

Input and Output Capacitors

The CM3202−02 requires that at least a 220 mF electrolytic capacitor be located near the VIN pin for stability and to maintain

the input bus voltage during load transients. An additional 4.7 mF ceramic capacitor between the VIN and GND, located as close

as possible to those pins, is recommended to ensure stability.

At a minimum, a 220 mF electrolytic capacitor is recommended for the V

DDQ

output. An additional 4.7 mF ceramic capacitor

between the V

DDQ

and GND, located very close to those pins, is recommended.

At a minimum, a 220 mF electrolytic capacitor is recommended for the V

output. This capacitor should have low ESR to

achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice.

In addition, place a 4.7 mF ceramic capacitor between the V

pin and GND, located very close to those pins. The total ESR

must be low enough to keep the transient within the V

window of 40 mV during the transition for source to sink. An average

current step of ±0.5 A requires:

ESR t

40mV

1A

+ 40mW

Both outputs will remain stable and in regulation even during light or no load conditions.

The general recommendation for circuit stability for the CM3202−02 requires the following:

1. C

= C

DDQ

= C

= 220 mF/4.7 mF for the full temperature range of –40 to +85°C.

2. C

= C

DDQ

= C

= 100 mF/2.2 mF for the temperature range of –25 to +85°C.

CM3202−02

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APPLICATION INFORMATION (Cont’d)

Adjusting VDDQ Output Voltage

The CM3202−02 internal bandgap reference is set at 1.25 V. The V

DDQ

voltage is adjustable by using a resistor divider, R1

and R2:

DDQ

+ V

ADJ

R1 ) R2

where V

ADJ

= 1.25 V. The recommended divider value is R

= R

= 10 kW for DDR−1 application, and R1 = 4.42 kW,

R2 = 10 kW for DDR−2 application (V

DDQ

= 1.8 V, V

= 0.9 V).

Shutdown

ADJSD also serves as a shutdown pin. When this is pulled high (SHDN_H), both the VDDQ and the VTT outputs tri−state

and could sink/source less than 10 mA. During shutdown, the quiescent current is reduced to less than 0.5 mA, independent

of output load.

It is recommended that a low leakage Schottky diode be placed between the ADJSD Pin and an external shutdown signal

to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the CM3202−02

is again enabled.

Current Limit and Over−temperature Protection

The CM3202−02 features internal current limiting with thermal protection. During normal operation, V

DDQ

limits the output

current to approximately 2 A and V

limits the output current to approximately ±2 A. When V

is current limiting into a hard

short circuit, the output current folds back to a lower level (~1 A) until the over−current condition ends. While current limiting

is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package.

If the junction temperature of the device exceeds 170°C (typical), the thermal protection circuitry triggers and tri−states both

VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120°C the CM3202−02 returns to normal

operation.

Typical Thermal Characteristics

The overall junction to ambient thermal resistance (q

) for device power dissipation (P

) primarily consists of two paths

in the series. The first path is the junction to the case (q

) which is defined by the package style and the second path is case

to ambient (q

) thermal resistance which is dependent on board layout. The final operating junction temperature for any

condition can be estimated by the following thermal equation:

JUNC

+ T

AMB

) P

) ) P

)

+ T

AMB

) P

)

When a CM3202−02 using WDFN8 package is mounted on a double−sided printed circuit board with four square inches

of copper allocated for “heat spreading,” the q

is approximately 55°C/W. Based on the over temperature limit of 170°C with

an ambient temperature of 85°C, the available power of the package will be:

170° C * 85° C

55° CńW

+ 1.5W

P1-P3 P4-P6 P7-P9 P10-P11

CM3202-02DE

Mfr. #:

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Manufacturer:

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Description:

IC REG CONV DDR 2OUT 8WDFN

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CM3202-02DE

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