MAX3430
±80V Fault-Protected, Fail-Safe,
1/4-Unit Load, +3.3V RS-485 Transceiver
10 ______________________________________________________________________________________
stage, provides immediate protection against short cir-
cuits over the whole common-mode voltage range. The
second, a thermal shutdown circuit, forces the driver
outputs into a high-impedance state if the die tempera-
ture exceeds +160°C. Normal operation resumes when
the die temperature cools by +140°C, resulting in a
pulsed output during continuous short-circuit conditions.
Hot-Swap Capability
Hot-Swap Inputs
Inserting circuit boards into a hot, or powered backplane
may cause voltage transients on DE, RE, and receiver
inputs A and B that can lead to data errors. For example,
upon initial circuit board insertion, the processor under-
goes a power-up sequence. During this period, the high-
impedance state of the output drivers makes them
unable to drive the MAX3430 enable inputs to a defined
logic level. Meanwhile, leakage currents of up to 10µA
from the high-impedance output, or capacitively coupled
noise from V
CC
or GND, could cause an input to drift to
an incorrect logic state. To prevent such a condition from
occurring, the MAX3430 features hot-swap input circuitry
on DE to safeguard against unwanted driver activation
during hot-swap situations. When V
CC
rises, an internal
pulldown circuit holds DE low for at least 10µs, and until
the current into DE exceeds 200µA. After the initial
power-up sequence, the pulldown circuit becomes
transparent, resetting the hot-swap tolerable input.
Hot-Swap Input Circuitry
At the driver enable input (DE), there are two NMOS
devices, M1 and M2 (Figure 9). When V
CC
ramps from
0, an internal 15µs timer turns on M2 and sets the SR
latch, which also turns on M1. Transistors M2, a 2mA
current sink, and M1, a 100µA current sink, pull DE to
GND through a 5.6kΩ resistor. M2 pulls DE to the dis-
abled state against an external parasitic capacitance
up to 100pF that may drive DE high. After 15µs, the
timer deactivates M2 while M1 remains on, holding DE
low against three-state leakage currents that may drive
DE high. M1 remains on until an external current source
overcomes the required input current. At this time, the
SR latch resets M1 and turns off. When M1 turns off, DE
reverts to a standard, high-impedance CMOS input.
Whenever V
CC
drops below 1V, the input is reset.
