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89KTPES12N3

P1-P3P4-P4
This document provides an overview of and insight into the contents of the full 89EBPES12N3 Evaluation
Board User Manual which is available through IDT's secure access technical documentation portal.
To gain access to the full version of this document and other technical collateral housed at the myIDT secure
portal, please contact ssdhelp@idt.com or your local IDT Sales contact.
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2006 Integrated Device Technology, Inc.
IDT
™
89EBPES12N3 Rev. 1.0
Evaluation Board
User Manual
Table of Contents and Overview
Notes
89EBPES12N3 Evaluation Board Manual i March 8, 2006
Table of Contents
1 Description of the EB12N3 Eval Board
Introduction..................................................................................................................................1-1
Board Features............................................................................................................................1-2
Hardware............................................................................................................................1-2
Software.............................................................................................................................1-2
Other ..................................................................................................................................1-2
Revision History...........................................................................................................................1-3
2 Installation of the EB12N3 Eval Board
EB12N3 Installation .....................................................................................................................2-1
Hardware Description ..................................................................................................................2-1
Host System.......................................................................................................................2-1
Reference Clocks ........................................................................................................................2-3
Power Sources ............................................................................................................................2-4
External Power Source.......................................................................................................2-4
PCI Express Serial Data Transmit Termination Voltage Regulator.....................................2-4
PCI Express Digital Power Voltage Regulator....................................................................2-4
PCI Express Analog Power Voltage Regulator ..................................................................2-4
Core Logic Voltage Regulator ............................................................................................2-4
Required Jumpers..............................................................................................................2-4
Reset ...........................................................................................................................................2-5
Fundamental Reset............................................................................................................2-5
Boot Configuration Vector............................................................................................................2-5
SMBus Interfaces ........................................................................................................................2-7
SMBus Slave Interface.......................................................................................................2-7
SMBus Master Interface.....................................................................................................2-9
JTAG Header...............................................................................................................................2-9
Attention Buttons .......................................................................................................................2-10
Miscellaneous Jumpers, Headers..............................................................................................2-10
LEDs..........................................................................................................................................2-10
PCI Express Connector .............................................................................................................2-12
Locations of Connectors, Jumpers, and Switches.....................................................................2-14
3 Software for the EB12N3 Eval Board
Introduction..................................................................................................................................3-1
Device Management Software.....................................................................................................3-1
4 Schematics
Schematics ..................................................................................................................................4-1
Notes
89EBPES12N3 Evaluation Board Manual 1 - 1 March 8, 2006
Chapter 1
Description of the EB12N3
Eval Board
Introduction
The 89HPES12N3 switch (also referred to as PES12N3 in this manual) is a member of IDT’s PCI
Express standard (PCIe) based line of products. It is a 3 port switch, with 4 serial lanes per port (x4). One
upstream port is provided for connecting to the root complex (RC), and two downstream ports are available
for connecting to PCIe endpoints or to another switch. More information on this device can be found in the
89HPES12N3 User Manual.
The 89EBPES12N3 Evaluation Board (also referred to as EB12N3 in this manual) provides an evalua-
tion platform for the PES12N3 switch. It is also a cost effective way to add a PCIe downstream port (x4) to
an existing system with a limited number of PCIe downstream ports. The EB12N3 eval board is designed to
function as an add-on card to be plugged into a x4 PCIe slot available on a motherboard hosting an appro-
priate root complex and microprocessor(s). The EB12N3 is a vehicle to test and evaluate the functionality of
the PES12N3 chip, and it can also play an important role for customers to get a headstart on software
development while they await the arrival of their own hardware. It is also used inside IDT to reproduce
system level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block
diagram representing the main parts of the EB12N3 board.
Figure 1.1 Functional Block Diagram of the EB12N3 Eval Board
Voltages on board
+12 V
5 V
External Power
Connector
(optional)
+3.3 V
+1.5 V
+1.0 V
+
JTAG
Header
Main
Reset
I/O Expander
PCA9555
PCIe x4 Upstream Edge
EPROM
24LC512
24LC512
EPROM
SMBUS
HEADER
PES12N3
PCI Express
Switch
MIC2951B
Controller
Dual Power
PCIe x4 Downstream Slot
PCIe x4 Downstream Slot
x4
x4
x4
25 MHz
SSC Clock
Buffer
Clock
Fanout
HCSL CLK
SMBus
P1-P3P4-P4

89KTPES12N3

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