PL680-37OC-R

38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 4
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL MIN. MAX. UNITS
Supply Voltage V
DD
4.6 V
Input Voltage, dc V
I
-0.5 V
DD
+0.5 V
Output Voltage, dc V
O
-0.5 V
DD
+0.5 V
Storage Temperature T
S
-65 150
C
Ambient Operating Temperature* T
A
-40 85
C
Junction Temperature T
J
125
C
Lead Temperature (soldering, 10s) 260
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.* Operating Temperature is guaranteed by design for all parts
(COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
Parallel Fundamental Mode, 3.3V 19 40
Crystal Resonator
Frequency
F
XIN
Parallel Fundamental Mode, 2.5V 19 28.125
MHz
Crystal Loading Rating C
L (xtal)
18 pF
Crystal Shunt Capacitance C
0 (xtal)
5 pF
Recommended ESR R
E
AT cut 30 Ω
Note: Crystal Loading rating: 18 pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this
load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more
load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain.
3. General Electrical Specifications
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
38MHz<F
OUT
<100MHz 65/45/30
LVPECL/LVDS
/LVCMOS
100MHz<F
OUT
<320MHz 80/60/40
Supply Current,
Dynamic
(Loaded Outputs)
I
DD
LVPECL/LVDS 320MHz<F
OUT
<640MHz 90/70
mA
Operating Voltage V
DD
2.25** 3.63 V
Output Clock
Duty Cycle
@ 50% V
DD
(LVCMOS)
@ 1.25V (LVDS)
@ V
DD
1.3V (LVPECL)
45 50 55 %
Short Circuit Current
50
mA
Stabilization Time * T
STB
From power valid 10 ms
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not production tested to any specific limits. The 2.5V operating supply voltage, denoted by (**), is limited to a
maximum VCO frequency of 450 MHz.
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 5
4. Jitter Specifications
PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS
106.25MHz 0.4 0.5
156.25MHz 0.4 0.5
212.5MHz 0.4 0.5
312.5MHz 0.4 0.5
Integrated jitter
RMS
Integrated 12kHz to 20MHz
622.08MHz 0.4 0.5
ps
106.25MHz 3 5
156.25MHz 3 5
212.5MHz 3 5
312.5MHz 3 5
Period jitter
RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
622.08MHz 6 8
ps
106.25MHz 20 30
156.25MHz 20 30
212.5MHz 20 30
312.5MHz 20 30
Period jitter
Peak-to-Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
622.08MHz 40 50
ps
5. Phase Noise Specifications
PARAMETERS FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M UNITS
106.25MHz -66 -96 -122 -132 -126 -144 -150
156.25MHz -62 -92 -120 -132 -128 -140 -150
212.5MHz -62 -92 -118 -126 -120 -140 -150
312.5MHz -59 -85 -117 -128 -125 -139 -148
Phase Noise
relative to
carrier (typical)
622.08MHz -49 -84 -111 -120 -118 -128 -138
dBc/Hz
6. LVCMOS Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 30 mA
Output Drive Current
I
OL
V
OL
= 0.4V, V
DD
= 3.3V 30 mA
0.3V ~ 3.0V with 15 pF load 0.7 ns
Output Clock Rise/Fall Time T
R
/T
F
20%-80% with 50 Load 0.3 ns
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 6
7. LVDS Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
Output Differential Voltage V
OD
247 355 454 mV
V
DD
Magnitude Change
V
OD
-50 50 mV
Output High Voltage V
OH
1.4 1.6 V
Output Low Voltage V
OL
0.9 1.1 V
Offset Voltage V
OS
1.125 1.2 1.375 V
Offset Magnitude Change
V
OS
R
L
= 100Ω
(see figure)
0 3 25 mV
Power-off Leakage I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1 10
uA
Output Short Circuit Current I
OSD
-5.7 -8 mA
8. LVDS Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
Differential Clock Rise Time t
r
0.2 0.7 1.0 ns
Differential Clock Fall Time t
f
R
L
= 100Ω
C
L
= 10 pF
(see figure)
0.2 0.7 1.0 ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test CircuitLVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF

PL680-37OC-R

Mfr. #:
Manufacturer:
Description:
Standard Clock Oscillators 38 - 640MHz Low Phase Noise XO
Lifecycle:
New from this manufacturer.
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